U-boot中LPDDR4关键参数的意义

LPDDR4关键参数意义

#!/usr/bin/env python3
import struct

# 手动配置： 0-disable; 1-enable
manual_config = 0

# DDR的数据位宽
data_width = 32

# channel个数
channel = 1

# LPDDR4 PHY时钟速度
speed = 3200
membus_clock = 600
# 使能内部PLL展频
membus_ssc = 0
# 当有2个DRAM controller时，使用的interleaving size
intlv_size = 8 # 128Mbyte by 1. 128*8=1024Mbyte
# debug信息的打印
debug = 0
total_size = 2048
channel0_size = 1024
channel1_size = 1024
# DRAM的RANK个数
num_chip = 2
# RANK size
chip_size = 16
# 行地址线的数量
chip_num_row = 16
# 列地址线的数量
chip_num_col = 10
# RANK density
density = 8

manual_dramvalue = 0
# DRAM VREF(DQ)的范围：0或者1
dram_vref_range = 0
dram_ca_vref_range = 0
rclk_freq = 25
reqq_depth = 30
wdq_depth = 64
# DRAM RANK interleaving On/off. 对于2 RANK DRAM可以使用
rank_interleaving = 0
# DRAM Channel interleaving On/off
channel_interleaving = 0
meso_synchronizer = 1
mrr_byte_lane = 5
byte_lane_inversion = 0
# VREF在DRAM初始化时的值
initial_dram_vref = 20
# CA VREF在DRAM初始化时的值
initial_dram_ca_vref = 25
# Read Post-Amble length: 0: 0.5*tCK; 1: 1.5*tCH
lpddr4_rpst = 0
# Write Post-Amble length: 0: 0.5*tCK; 1: 1.5*tCH
lpddr4_wpst = 0
# Read Pre-Amble type: 0: Static; 1: Toggle
lpddr4_rpre = 1
# Read Pre-Amble type: 0: Reserved; 1: 2*tCK
lpddr4_wpre = 1 # 2133 over 1
# DRAM On-die-termination for CA
lpddr4_ca_odt = 6
# DRAM On-die-termination for DQ
lpddr4_dq_odt = 4
# DRAM Drive strength for DQ
lpddr4_dq_dds = 6
read_dbi = 1
write_dbi = 1
write_odt = 1
ca_odt = 1
# 1: Control CKE to all the ranks at the same time.
# 0: Control CKE to each rank independently.
single_cke = 0
extra_rtw = 0
init_zq_calibration = 1
t_refipb = 3904000
t_refiab = 488000
t_zqcal = 1000000
t_fc = 200000
t_vrcg_disable = 100000
# The MR4 sensing function periodically reads the temperature information of the MR4 
# register of LPDDR4 and automatically sets the refresh time according to the tem.
mr4_sensing = 1
mr4_sensing_period = 32000 # us
zq_calibration = 1
zq_calibration_period = 48000 # us
periodic_training = 1
periodic_training_period = 640000 # us
dynamic_power_down = 1
dynamic_self_refresh = 1
regional_clock_gating = 1
phy_clock_gating =  1
dram_clock_gating = 1

manual_socvalue = 0
# SoC初始化时的VREF值 
initial_soc_vref = 0x11
# SoC时钟信号的输出驱动能力: 0~7对应不同的电阻阻值
clock_dds = 5
# CS信号的驱动能力调节：0~7
cs_dds = 5
# DQ/DQS信号的驱动能力
cpu_ds_dds = 5
# On-die-termination电阻阻值
cpu_odt = 4
dll_start_point = 0x10
dll_ctrl_ref = 8
zq_clk_div = 7
# 0: Fast; 1: Slow
dq_slew_control = 0

#training的enable和disable
manual_option = 0
ca_train = 0
rd_train = 1
wr_train = 1
prbs_train = 1
soc_vref_train = 1
dram_vref_train = 1

如需对某一参数做针对性测试，可以在修改参数后执行该配置文件，然后重新编译u-boot。

DRAM测试工具：memtester

memtester网站：https://linux.die.net/man/8/memtester

memtester下载：http://pyropus.ca/software/memtester/

 

题外话：

LPDDR4带宽（bandwidth或者叫做throughput）的计算方法：

对于1颗LPDDR4，1个channel, 32bit位宽，频率为2133Mhz, 其带宽为：

2（DDR，双边沿取数据）* 1（1个channel）* 32（位宽）* 2133（频率）/ 8（1byte=8bit）/ 1000 = 17.064 GB/s

需要处理的数据量越大，对DRAM的带宽要求越高。DRAM带宽是系统能否流畅运行的关键参数之一。