Verilog实现任意比特位数的有符号加法器

module sign_adder #
(
    parameter N = 4
)(
    input   wire    [N-1:0] a,b,
    
    output  reg     [N-1:0] sum
);

reg sign_a, sign_b, sign_sum;
reg [N-2:0] mag_a, mag_b, mag_sum, max, min;

always@(a,b)  begin
    sign_a = a[N-1];
    sign_b = b[N-1];
    mag_a = a[N-2:0];
    mag_b = b[N-2:0];
    
    if(mag_a > mag_b) begin
        sign_sum = sign_a;
        max = mag_a;
        min = mag_b;
    end
    else begin
        sign_sum = sign_b;
        max = mag_b;
        min = mag_a;
    end
    
    if(sign_a == sign_b)
        mag_sum = max + min;
    else 
        mag_sum = max - min;
    
    sum = {sign_sum, mag_sum};
end

endmodule

module tb_sign_adder();
reg  [4:0] a,b;
wire [4:0] sum;

initial begin
    a = 0;
    b = 0;
    #30 a = 5'b10100;
    #30 b = 5'b00011;
    #30 a = 5'b00100;
    #30 b = 5'b00101;
end

sign_adder #(5) sign_adder_inst
(
    .a(a),
    .b(b),
    .sum(sum)
);

endmodule