数字IC设计：绪论Introduction

写在前面：本文为学习笔记整理，参考资料主要是Neil Weste和David Harris写的《CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition)》。有空我再翻译出对应的中文版。

[Abbreviations]
1. VLSI: Very Large Scale Integration, >10k gates
2. CMOS: Complementary Mental Oxide Semiconductor
3. MOSFET: Metal-Oxide-Semiconductor Field Effect Transistor

1 Two transistor types

• Bipolar transistors:
  ➀ Two types: npn & pnp
  ➁ Current-driven: small I_b -> large I_e & I_c
  ➂ Limited: Base currents I_b limit integration density

• MOSFET:
  ➀ Two types: NMOS & PMOS
  ➁ Voltage-driven: V_g -> I_ds
  ➂ Advantages: Low power allows very high integration

2 Moore’s Law

• “Gorden Moore predicts that the number of components on a computer chip doubled every 18-24 months, while the price remained.”

  => Mininum feature size shrinks 30% every 2-3 year.

The limit for minimum feature size: No smaller than the distant between two silicon atoms, i.e. 2.35Å(Angstrom) = 2.35*10^-10m = 0.235nm

3 P-N Junctions & Diode Equation

• A junction between p-type and n-type semiconductor forms a diode.

• For an ideal diode: I_d = I_s(e^V_D/φ_T - 1), where Thermal voltage φ_T = kT/q = 26mV at 300K, I_s is the saturation current of the diode, V_D is the voltage across the diode.

  Characteristics of P-N Junctions & Diode: Current flows only in one direction from p (anode) to n (cathode). Specifically, for an diode:
  1. A forward-bias lowers the potential barrier allowing carriers to flow across the diode junction.
  2. A reverse-bias raises the potential barrier & the diode becomes non-conducting.

4 MOS Operations

4.1 NMOS Cross Section

• 4 terminals: gate, source, drain, body

• Gate-SiO₂-Body forms Mental-Oxide-Semiconductor capacitor. (Note that gate ≠ mental anymore, gate = polysilicon)

• Body is commonly tied to GND.

4.2 MOS Transistors Types & Symbols

4.3 Three Modes of NMOS Operation: Cutoff, Linear, Saturation

• 1 Cut-off Mode
  $$V_{gs}\le V_T\text{(no channel)}$$
  => I_ds = 0
  => The junctions between the body and the source or drain are zero-biased or reverse-biased.
  => Little or no current flows

• 2 Linear/Resistive/Triode/Unsaturated Mode
  $$\{\begin{array}{l}{V}_{gs}>V_T\text{(channel forms)}\\ V_{ds}\le V_{gs}-V_T\end{array}$$
  => An inversion region of n-type called the channel connects the source and drain, creating a conductive path and turning the transistor ON.
  => I_ds increases with V_gs
  => Similar to linear resistor

• 3 Saturation Mode
  $$\{\begin{array}{l}{V}_{gs}>V_T\\ V_{ds}>V_{gs}-V_T\text{(Channel pinched-off)}\end{array}$$
  => The channel is no longer inverted near the drain and becomes pinched-off.
  => Ids is controlled only by the gate voltage and ceases to be influenced by the drain.
  => Similar to current source

Pinched-off refers to when V_ds > V_gs - V_T (for NMOS), the channel is no longer inverted near the drain, but conduction is still brought about by the drift of electrons under the influence of the positive drain voltage. As electrons reach the end of the channel, they are injected into the depletion region near the drain and accelerated toward the drain.

Summary of 3 Modes of CMOS Operation:

1. Cutoff Mode:
   $$\begin{gathered} I_{ds}=0 \\ NMOS:V_{gs}\le V_T \\ PMOS:V_{gs}\ge V_T \end{gathered}$$
2. Linear/Resistive/Triode/Unsaturated Mode:
   $$\begin{gathered} I_{ds}=\beta [(V_{gs}-V_T)\cdot V_{ds}-\frac{V_{ds}^2}{2}]\text{ (Ideal devices or long channel devices)} \\ NMOS:\{\begin{array}{l}{V}_{gs}>V_T\\ V_{ds}<V_{gs}-V_T\end{array} \\ PMOS:\{\begin{array}{l}{V}_{gs}<V_T\\ V_{ds}>V_{gs}-V_T\end{array} \end{gathered}$$
3. Saturation Mode:
   $$\begin{gathered} I_{ds}=\frac{1}{2}\beta (V_{gs}-V_T{)}^2\text{ (Ideal devices or long channel devices)} \\ {I}_{ds}=\frac{1}{2}\beta (V_{gs}-V_T{)}^2\cdot (1+\lambda V_{ds})\text{ (With channel-length modulation)} \\ {I}_{ds}=v_{max}\cdot C_{ox}\cdot W(V_{gs}-V_T)\text{ (Velocity saturation)} \\ NMOS:\{\begin{array}{l}{V}_{gs}>V_T\\ V_{ds}>V_{gs}-V_T\end{array} \\ PMOS:\{\begin{array}{l}{V}_{gs}<V_T\\ V_{ds}<V_{gs}-V_T\end{array} \end{gathered}$$
   Note: long-channel devices: L>0.25um; short-channel devices: L<0.25um

5 MOS(FET) Transistor As Switch

• Switch ON: when gate voltage V_gs > threthold voltage V_T, a conducting channel is developed between drain and source. And the voltage difference between drain and source causes current to flow between the two regions. V_gs modulated the conductivity of the channel where the larger the voltage difference between gate and source, the smaller the channel resistance and the larger the current.

• Switch OFF: when V_gs < V_T, no such channel exists, and the switch is considered OFF.

6 The Threshold Voltage

The threshold voltage $V_T$: The value of V_gs where strong inversion occurs is called V_T
(Related non-linear theory such as Body Effect will be introduced in other posts.)

7 Signal Strength

• Strength of signal: How close it approcimates ideal voltage source

• Strongest 0/1: GND/VDD rails

7.1 Pass Transistors

• NMOS passes strong 0: when g=1 &d=0, s can be approximate $G_{nd}$.
  NMOS passes degraded/weak 1: when g=1 & d=1, s can be as high as $V_{dd}-V_T$, otherwise OFF.

• PMOS passes strong 1: when g=0 & d=1, s can be approximate $V_{dd}$
  PMOS passes degraded/weak 0: when g=0 & d=0, s can be as low as $|V_T|$, otherwise OFF.

See the graph below, pass transistors degraded outputs.

7.2 Transmission Gates

=> Pass both strong 0 and strong 1

Other transimission gates symbols:

Application example: 2-input multiplexer:

8 Complementary CMOS

• The inputs drive the Gate terminals of NMOS transistors in the pull-down network.

• The inputs drive the Gate terminals of PMOS transistors in the pull-up network.

=> Reason: NMOS only passes 0 and PMOS only passes 1 -> Outputs are always strong driven -> Fully Restored Logic Gate

9 MOS Capacitor

1. MOS Capacitor: Gate-Insulator-Body capacitor

2. 3 operation modes:
   ➀ Accumulation: when $V_{gb}<0$, the negative charge on the gate causes the mobile positive charges holes to be attracted to the region beneath the gate.
   ➁ Depletion: when $0<V_{gb}<1$, the holes in the body are repelled from the region directly beneath the gate, resulting in depletion region forming below the gate.
   ➂ Inversion: when $V_{gb}>V_T$, the holes are repelled further and a small number of free electrons in the body are attracted to the region beneath the gate.

1. $\beta =\mu \cdot C_{ox}\cdot \frac{W}{L}=\mu \cdot \frac{{\epsilon }_{ox}}{t_{ox}}\cdot \frac{W}{L}$
2. We assume $\frac{{\mu }_n}{{\mu }_p}=2$, then PMOS must be wider than NMOS to provide the same current. => typically $\frac{W_p}{W_n}=2$

10 MOS Capacitor Model

$$\{\begin{array}{l}\text{Gate Capacitance}\{\begin{array}{l}\text{Intrinsic capacitance}\\ \text{Overlap capacitance}\end{array}\text{=> Good Cap.}\\ \text{Diffusion Capacitance/Parastic Capacitance => Undesirable Cap.}\end{array}$$

10.1 Gate Capacitance $C_g$

1. High $C_g$ is required to obtain high $I_{ds}$ because it’s neccessary to attract charge to invert channel.
   $$C_g=C_{permicron}\cdot W=C_{ox}\cdot W\cdot L=\frac{{\epsilon }_{ox}}{t_{ox}}\cdot W\cdot L$$
2. For a particular process, the min. manufacturable length L results in greatest speed and lowest power consumption.

（1）Intrinsic Capacitance $C_g$: over the channel
$$C_g=C_{gs}+C_{gd}+C_{gb}$$

• Cutoff Mode: no channel forms.
  $$\{\begin{array}{l}{C}_{gb}=C_o=C_{ox}\cdot W\cdot L\\ C_{gs}=C_{gd}=0\end{array}$$
• Linear Mode: channel forms and it’s connected to S and D.
  $$\{\begin{array}{l}{C}_{gb}=0\\ C_{gs}=C_{gd}=\frac{C_o}{2}=\frac{1}{2}{C}_{ox}\cdot W\cdot L\end{array}$$
• Saturation Mode: the channel pinches off.
  $$\{\begin{array}{l}{C}_{gb}=0\\ C_{gd}=0\\ C_{gs}=\frac{2}{3}{C}_o=\frac{2}{3}{C}_{ox}\cdot W\cdot L\end{array}$$

（2）Overlap Capacitances $C_{gs(overlap)}$

Overlap capacitance becomes relatively more important for shorter channel transistors because it’s a larger fraction of the total.

$$\{\begin{array}{l}{C}_{gs(overlap)}=C_{gsol}\cdot W\\ C_{gd(overlap)}=C_{gdol}\cdot W\end{array}$$

10.2 Diffusion/Parastic Capacitance

Diffusion capacitance is also called parastic capacitance, which arises from reverse-biased p-n junctions between source or drain diffusion and body.
$$\{\begin{array}{l}{C}_g=C_{sb}=C_{db}\text{ for contacted source and drain regions}\\ C_{sb}=AS\cdot C_{jbs}+PS\cdot C_{jbssw}\end{array}$$
where $AS$(Area) $=W\cdot D$, $PS$(Perimeter) $=2W+2D$, $D$ is the length of source diffusion.

The diffusion capacitance of the uncontacted source or drain is less due to the smaller ares.