2. （开发流程）组合逻辑3_8译码器实现与相关语法基础

1. 设计定义

三八译码器，顾名思义，三位输入，八位输出；即通过三根信号线控制八种输出情况。

2. FPGA

2.1 打开vivado，创建项目

2.2 创建设计文件

module decoder_3_8(
    a,
    b,
    c,
    out
);
    input a;
    input b;
    input c;
    output[7:0] out;
    
    reg[7:0] out;

    //以always块描述的信号赋值，被赋值对象必须定义为reg类型
    
    //{a, b, c}变成了一个三位信号， 这种操作叫做位拼接
    //wire[3:0] d;
    //assign d = {a, 1'b0, b, c};

    always@(*) begin
        case({a, b, c})
            3'b000: out = 0000_0001;
            3'b001: out = 0000_0010;
            3'b010: out = 0000_0100;
            3'b011: out = 0000_1000;
            3'b100: out = 0001_0000;
            3'b101: out = 0010_0000;
            3'b110: out = 0100_0000;
            3'b111: out = 1000_0000;
        endcase
    end

endmodule

2.3 创建仿真文件

`timescale 1ns/1ns

module decoder_3_8_tb();

    reg s_a;
    reg s_b;
    reg s_c;
    wire[7:0] out;
    
    decoder_3_8 decoder_3_8(
        .a(s_a),
        .b(s_b),
        .c(s_c),
        .out(out)
    );
    
    initial begin
        s_a = 0; s_b = 0; s_c = 0;
        #200;
        s_a = 0; s_b = 0; s_c = 1;
        #200;
        s_a = 0; s_b = 1; s_c = 0;
        #200;
        s_a = 0; s_b = 1; s_c = 1;
        #200;
        s_a = 1; s_b = 0; s_c = 0;
        #200;
        s_a = 1; s_b = 0; s_c = 1;
        #200;
        s_a = 1; s_b = 1; s_c = 0;
        #200;
        s_a = 1; s_b = 1; s_c = 1;
        #200;
		$stop;
    end

endmodule

2.4 查看波形，调试代码

2.5 布置引脚

查看引脚编号

 

2.6 上板验证