数字电路设计自动化作业—1
1、七人投票表决电路
Verilog代码如下:
module vote_7(
input [6:0] Vote,
input Reset,
output Pass);
integer i;
reg [2:0] vote_count;
always @(*) begin
if (Reset)
begin
vote_count = 3'd0;
end
else
begin
vote_count = 3'd0;
for (i=0;i<7;i=i+1)
begin
if (Vote[i] == 1) vote_count = vote_count + 1'd1;
end
end
end
assign Pass = (vote_count >= 3'd4) ? 1 : 0;
endmodule
测试代码如下:
//vote_7_tb
`timescale 1 ns/1 ns
module vote_7_tb();
reg [6:0] Vote;
reg Reset;
wire Pass;
vote_7 my_vote_7(
.Vote(Vote),
.Reset(Reset),
.Pass(Pass));
initial
begin
Vote=7'b0000001; Reset=0;
#5 Vote=7'b0000111; Reset=1;
#5 Vote=7'b0001111; Reset=0;
#5 Vote=7'b0011111; Reset=0;
#5 Vote=7'b0111111; Reset=0;
#5 Vote=7'b1111111; Reset=0;
#5 Vote=7'b1100111; Reset=0;
#5 Vote=7'b1100101; Reset=1;
#5 Vote=7'b1110101; Reset=0;
#5 $stop;
end
endmodule
仿真波形如下(清晰显示请点开放大):
2、七人抢答电路
Verilog代码如下:
module responder(
input [6:0] vote,
input start,
input reset,
output reg nag,
output reg [2:0] rsp
);
always @(*) begin
if (reset)
begin
nag = 1'b0;
rsp = 3'b0;
end
else if (start)
begin
case (vote)
7'b0000001: begin rsp = 3'b001; nag = 1'b0; end
7