KV260 进阶开发（PYNQ驱动开发+Pixel Pack）

最新推荐文章于 2025-03-04 00:20:46 发布

hi94

最新推荐文章于 2025-03-04 00:20:46 发布

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分类专栏： PYNQ 文章标签：算法驱动开发模型部署深度学习人工智能

本文链接：https://blog.csdn.net/DongDong314/article/details/142000253

版权

1. 简介

2. PixelPacker HLS 实现

2.1 PixelPacker HLS 源码

3.1 PixelPacker Py 源码

1. 简介

本文讨论在 PYNQ 框架下，使用 Python 驱动 Vitis HLS Kernel。
使用 Registermap 也可以完成驱动，即直接操作所有寄存器。
通过 Python 方式编写的驱动更直观，可以理解为对 Registermap 的封装。
Registermap 和 Python 驱动，底层都是调用 MMIO 的读写。

2. PixelPacker HLS 实现

2.1 PixelPacker HLS 源码

Pixel Packerhttps://github.com/Xilinx/PYNQ/tree/master/boards/ip/hls/pixel_pack

#include <ap_fixed.h>
#include <ap_int.h>
#include "hls_stream.h"
#include <ap_axi_sdata.h>

typedef ap_axiu<24,1,0,0> narrow_pixel;
typedef ap_axiu<32,1,0,0> wide_pixel;

typedef hls::stream<narrow_pixel> narrow_stream;
typedef hls::stream<wide_pixel>   wide_stream;

#define V_24 	0
#define V_32 	1
#define V_8 	2
#define V_16 	3
#define V_16C 	4

void pixel_pack(narrow_stream& stream_in_24 ,
				  wide_stream& stream_out_32,
				  	  	   int mode,
				    ap_uint<8> alpha) {
#pragma HLS INTERFACE mode=axis register_mode=both depth=24 port=stream_in_24  register
#pragma HLS INTERFACE mode=axis register_mode=both depth=24 port=stream_out_32 register
#pragma HLS INTERFACE mode=s_axilite    port=mode  register
#pragma HLS INTERFACE mode=s_axilite    port=alpha register
#pragma HLS INTERFACE mode=ap_ctrl_none port=return

	bool last = false;
	bool delayed_last = false;
	narrow_pixel in_pixel;
	wide_pixel out_pixel;
	switch (mode) {
	case V_24:
		while (!delayed_last) {
#pragma HLS pipeline II=4
			delayed_last = last;
			ap_uint<96> buffer;
			ap_uint<4> has_last;
			ap_uint<4> has_user;
			for (int j = 0; j < 4; ++j) {
				if (!last) {
					stream_in_24.read(in_pixel);
					buffer(j*24 + 23, j*24) = in_pixel.data;
					has_user[j] = in_pixel.user;
					has_last[j] = in_pixel.last;
					last = in_pixel.last;
				}
			}
			if (!delayed_last) {
				for (int i = 0; i < 3; ++i) {
					out_pixel.data = buffer(i*32 + 31, i*32);
					out_pixel.user = has_user[i];
					out_pixel.last = has_last[i+1];
					stream_out_32.write(out_pixel);
				}
			}
		}
		break;
	case V_32:
		while (!last) {
#pragma HLS pipeline II=1
			ap_uint<32> data;
			stream_in_24.read(in_pixel);
			data(23, 0) = in_pixel.data;
			data(31, 24) = alpha;
			out_pixel.data = data;
			out_pixel.last = in_pixel.last;
			out_pixel.user = in_pixel.user;
			last = in_pixel.last;
			stream_out_32.write(out_pixel);

		}
		break;
	case V_8:
		while (!delayed_last) {
#pragma HLS pipeline II=4
			delayed_last = last;
			bool user = false;
			ap_uint<32> data;
			for (int i = 0; i < 4; ++i) {
				if (!last) {
					stream_in_24.read(in_pixel);
					user |= in_pixel.user;
					last = in_pixel.last;
					data(i*8 + 7, i * 8) = in_pixel.data(7,0);
				}
			}
			if (!delayed_last) {
				out_pixel.user = user;
				out_pixel.last = last;
				out_pixel.data = data;
				stream_out_32.write(out_pixel);
			}
		}
		break;
	case V_16:
		while (!last) {
#pragma HLS pipeline II=2
			bool user = false;
			ap_uint<32> data;
			for (int i = 0; i < 2; ++i) {
				stream_in_24.read(in_pixel);
				user |= in_pixel.user;
				last = in_pixel.last;
				data(i*16 + 15, i*16) = in_pixel.data(16,0);
			}
			out_pixel.user = user;
			out_pixel.last = last;
			out_pixel.data = data;
			stream_out_32.write(out_pixel);
		}
		break;
	case V_16C:
		while (!last) {
#pragma HLS pipeline II=2
			bool user = false;
			ap_uint<48> data;
			for (int i = 0; i < 2; ++i) {
				stream_in_24.read(in_pixel);
				user |= in_pixel.user;
				last = in_pixel.last;
				data(i*24 + 23, i*24) = in_pixel.data;
			}
			ap_uint<32> out_data;
			ap_uint<9> out_c1 = ap_uint<9>(data(15,8))  + ap_uint<9>(data(39,32));
			ap_uint<9> out_c2 = ap_uint<9>(data(23,16)) + ap_uint<9>(data(47,40));
			out_data(7,0) = data(7,0);
			out_data(15,8) = out_c1(8,1);
			out_data(23,16) = data(31,24);
			out_data(31,24) = out_c2(8,1);
			out_pixel.user = user;
			out_pixel.last = last;
			out_pixel.data = out_data;
			stream_out_32.write(out_pixel);
		}
		break;
	}
}