Embeded IP Licensing

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Embedded Programmable-IPs provide high-performance, low-cost, and high utilization (99%+) , proven by existing leading customers and abundant full-mask tapeouts verified. Process layouts are ready in 0.18um, 0.13um, 0.11um, 65nm, 55nm, 40nm nodes at the leading foundries, and any cutting-edge cmos technologies. Manufacturing cost is less than 1 to 2 cents per k-LUT, in any geometry (row by column tile) layout configuration. Silicon size is as small as 0.8mm^2 for 1280 LUT for commonly available technology nodes in all foundries. Utilization (LUT) for actual designs are commonly up to 99%+. That makes it possible for building multi-million gates while high performance device for communication markets. This key differentiating technologies are licensable to IC companies or FPGA IC companies targetting communiction markets.

嵌入式可编程IP提供了高性能,低成本和高利用率(99%+),已被现有的领先客户证明并经过了验证的大量全掩码流片。 在领先的代工厂生产,可以使用0.18um,0.13um,0.11um,65nm,55nm,40nm节点以及任何尖端的cmos技术进行工艺布局。在任何几何形状(逐列瓦片)布局配置中,每K-LUT的制造成本不到1-2美分。对于所有铸造厂中的通用技术节点,对于1280 LUT而言,硅尺寸小至0.8mm ^ 2。 实际设计的利用率(LUT)通常高达99%以上。这使得建造数百万个门电路成为可能,同时又为通信市场提供了高性能的设备。这项关键的差异化技术可授权给针对通讯市场的芯片公司或FPGA 芯片公司。

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