115，Verilog-2005标准篇：verilog实用编译指令总结

Define类编译指令介绍:

`define <name> <string>



`ifdef <define_name>

   <statements>;

`elsif <define_name>

   <statements>;

`else

   <statements>;

`endif



`ifndef <define_name>

   <statements>;

`endif

例子：

`define DATA_WIDTH 16

`define DATA_WIDTH16



reg [`DATA_WIDTH-1:0] data;



`ifdef DATA_WIDTH8

   // If DATA_WIDTH8 was set, this would get compiled

`elsif DATA_WIDTH16

   // Since DATA_WIDTH16 is set, this does get compiled

`else

   // If DATA_WIDTH8 and DATA_WIDTH16 was not defined, this would be compiled

`endif

Include编译指令介绍

`include  "<file_name>"

例子：

`include "parameters.vh" // Include the contents of the parameters.vh file located in the current working directory.



`include "../data/ram_data.vh" // Include the contents of the ram_data.vh file in the relative directory ../data



`include "/export/vol1/sim_data/master.vh"// Include the contents of master.vh in the absolute directory /export/vol1/sim_data

timescale编译指令介绍：

// `timescale <units> / <precision>，仿真时需要该编译指令

// The units should be set to the base value in which time will be communicated to

// the simulator for that module.

// The precision is the minimum time units you wish the simulator to resolve. The

// smallest resolution value in all files and models compiled for simulation dictates

// the overall simulation resolution. In general for Xilinx FPGAs, a simulator

// resolution of 1ps is recommended since some components like the DCM require this

// resolution for proper operation and 1 ps is the resolution used for timing simulation.

//

// In general, this directive should appear at the top of the testbench, simulation models

// and all design files for a Verilog project.

`timescale 1 ns / 1 ns

`timescale 1 ns / 1 ps

`timescale 1 ns / 10 ps

`timescale 1 ns / 100 ps

`timescale 1 ps / 1 ps

`timescale 100 ps / 1 ps

例子：

  

`timescale 1 ns / 1ps

#1;           // Delays for 1 ns

#1.111;       // Delays for 1111 ps

#1.111111111; // Delays for 1111 ps since the resolution is more course than

              // what is specified, the delay amount is truncated

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