[HDLBits] Arithmetic Circuits

Exams/ece241 2014 q1c

Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0]. These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred.

module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
); 
 
    assign s = a + b;
    assign overflow = ( a[7] && b[7] && ~s[7] ) || (~a[7] && ~b[7] && s[7]);
endmodule

///
-7补码1001
-5补码1011
-7-5=-12
1001+1011=(1)0100
溢出为1
7补码0111
5补码0101
7+5=12
0111+0101=(0)1100
溢出为0
///