IMPL8. Analysis of the “bufif0/1“ which is a gate level description in Verilog

1. bufif0/1 truth table:

2. bufif0/1 schematic:

3.Spyglass Testcase.

case1. The bufif0 control pin is driven to 0;

a. code

top.v

logic.v

b.rpt

case2. The bufif1 control pin is driven to 1;

a. code

top.v  (as same upon)

logic.v

b.rpt

case3. The bufif0 control pin is driven to 1;

a.code

b.rpt

case4. The bufif0 control pin is driven to 1'bx;

a.code

b.rpt

case5. The bufif0 control pin is driven to 1'bz;

a. code

b.rpt

case5. In top drive the VDD to 1 and drive VSS to 0;

a. code

b. rpt

case6. the VDD and VSS is undriven.

a. code

b. rpt

Solution:

a.sgdc: set_case_analysis

b.rpt

Note: The bufif0/1 gate cell can be synthesis. This is the schematic of it.