VHDL语言testbench仿真的例子

参考：http://bbs.elecfans.com/jishu_418996_1_1.html

1.源代码

--六进制计数器的代码
Library ieee;  
use ieee.std_logic_1164.all;  
use ieee.std_logic_arith.all;  
use ieee.std_logic_unsigned.all;  
entity cnt6 is  
port  
  (clr,en,clk :in std_logic;  
  q  :out  std_logic_vector(2 downto 0)  
  );  
end entity;  
architecture rtl of cnt6 is  
signal tmp  :std_logic_vector(2 downto 0);  
begin  
  process(clk)  
--    variable q6:integer;  
    begin  
      if(clk'event and clk='1') then  
        if(clr='0')then  
          tmp<="000";  
        elsif(en='1') then  
          if(tmp="101")then  
            tmp<="000";  
          else  
            tmp<=unsigned(tmp)+'1';  
          end if;  
        end if;  
      end if;  
      q<=tmp;  
--      qa<=q(0);  
--     qb<=q(1);  
--     qc<=q(2);  
  end process;  
end rtl;  

2,testbench代码

 Quartus II 可以自动生成testbench代码固定格式。

如果自己不想写这些testbench的这些固定格式，可以在quartus里自动生成testbench文件的模板，然后往里面写信号就行了

步骤：processing->start->starttest bench template write

这里需要注意的是要在仿真选项里选择一个仿真工具，然后才会生成testbench

-- 六进制计数器testbench的代码
library ieee;  
use ieee.std_logic_1164.all;  
  entity cnt6_tb is   
end cnt6_tb;  
architecture rtl of cnt6_tb is  
  component cnt6  
    port(  
      clr,en,clk :in std_logic;  
      q  :out  std_logic_vector(2 downto 0)  
      );  
  end component;  
    signal clr  :std_logic:='0';  
  signal en   :std_logic:='0';  
  signal clk  :std_logic:='0';  
  signal  q   :std_logic_vector(2 downto 0);  
      constant clk_period :time :=20 ns;   
  begin  
    instant:cnt6 port map  
    (  
      clk=>clk,en=>en,clr=>clr,q=>q  
      );  
  clk_gen:process  
  begin      
    wait for clk_period/2;  
    clk<='1';   
    wait for clk_period/2;  
    clk<='0';  
  end process;  

  clr_gen:process  
  begin  
    clr<='0';  
    wait for 30 ns;  
    clr<='1';  
    wait;  
  end process;  
        en_gen:process  
  begin  
    en<='0';  
    wait for 50ns;  
    en<='1';  
    wait;  
  end process;  
end rtl;