Input_delay的-max/-min计算
Analog输出到Digital,针对analog/digital的边界进行时序约束:![模拟输出到数字](https://img-blog.csdnimg.cn/2021071414225021.PNG?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L0hVQU40NDE1,size_16,color_FFFFFF,t_70#pic_center)
input_delay | value |
---|
-max | T(ED)max - (T(AC)min -T(AB)max)+ T(BE)max |
-min | T(ED)min - (T(AC)max -T(AB)min) + T(BE)min |
Output_delay的-max/-min计算
Digital输出到Analog,针对analog/digital的边界进行时序约束:
![数字输出到模拟](https://img-blog.csdnimg.cn/20210714143534237.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L0hVQU40NDE1,size_16,color_FFFFFF,t_70)
output_delay | value |
---|
-max | T(DE)max - (T(AC)min -T(AB)max) |
-min | T(DE)min - (T(AC)max -T(AB)min) |
经验总结
依据电路混仿的数据:
1、代入公式计算后得到的input_delay/output_delay值;
2、确保SDC约束的-max值,大于混仿数据计算得到的-max值;
3、确保SDC约束的-min值,小于混仿数据计算得到的-min值;
set_input_delay | 同沿采集value(T*1.0) | 错沿采集value(T*0.5) |
---|
-max | CYCLE * 0.8 | CYCLE * 0.4 |
-min | CYCLE * 0.1 | CYCLE * 0.05 |
set_output_delay | 同沿采集value(T*1.0) | 错沿采集value(T*0.5) |
---|
-max | CYCLE * 0.8 | CYCLE * 0.4 |
-min | CYCLE * 0.1 | CYCLE * 0.05 |