串口发送5字节数据(状态机)学习笔记

 方法一:条件语句

// Create Date: 2024/04/04 12:08:41
// Design Name: hilary
// Module Name: uart_tx_data

//发送5个字节的数据,40位数据
//两种情况:
//空闲状态:上一次的数据发送完成
//发送数据请求信号到来,从低8位开始,依次发送数据
// 1.等待传输请求信号(Trans_Go)到来
// 2.Data40【7:0】给到uart_byte_tx的Data,同时产生Send_Go信号启动第一个字节的发送
// 3.等待Tx_Done信号二栋到来:① 40位(5个字节)数据是否发送完成
//                          ② 发完了回到1; 没发完启动下一个8位数据的发送

//状态机:
module uart_tx_data(
    Clk,
    Reset_n,
    Data40,
    Trans_Go,
    uart_tx,
    Trans_Done);

    input Clk;
    input Reset_n;
    input [39:0] Data40;
    input Trans_Go;
    output uart_tx;
    output reg Trans_Done;

    reg Send_Go;
    reg [7:0] Data;
    wire Tx_done;

    uart_byte_tx uart_byte_tx(
        .Clk(Clk),
        .Reset_n(Reset_n),
        .Data(Data),
        .Send_Go(Send_Go),
        .Baud_set(4),
        .uart_tx(uart_tx),
        .Tx_done(Tx_done)
        );
    
    reg [7:0] state;
    always @(posedge Clk or negedge Reset_n) begin
        if (!Reset_n) begin
            state <= 0;
            Data <= 0;
            Send_Go <= 0;
            Trans_Done <= 0;
        end
        else if (state == 0)begin
                    Trans_Done <= 0;
                    if(Trans_Go)begin
                        Data <= Data40[7:0];
                        Send_Go <= 1;
                        state <= 1;
                    end
                    else begin
                        Data <= Data;
                        Send_Go <= 0;
                        state <= 0;
                    end
              end
                
             else if (state == 1) begin
                        if (Tx_done) begin
                            Data <= Data40[15:8];
                            Send_Go <= 1;
                            state <= 2;
                        end
                        else begin
                            Data <= Data;
                            Send_Go <= 0;
                            state <= 1;
                        end
                  end

                  else if (state == 2) begin
                            if (Tx_done) begin
                                Data <= Data40[23:16];
                                Send_Go <= 1;
                                state <= 3;
                            end
                            else begin
                                Data <= Data;
                                Send_Go <= 0;
                                state <= 2;
                            end
                       end

                       else if (state == 3) begin
                            if (Tx_done) begin
                                Data <= Data40[31:24];
                                Send_Go <= 1;
                                state <= 4;
                            end
                            else begin
                                Data <= Data;
                                Send_Go <= 0;
                                state <= 3;
                            end
                       end

                            else if (state == 4) begin
                                if (Tx_done) begin
                                    Data <= Data40[39:32];
                                    Send_Go <= 1;
                                    state <= 5;
                                end
                                else begin
                                    Data <= Data;
                                    Send_Go <= 0;
                                    state <= 4;
                                end
                            end

                            else if (state == 5) begin
                                if (Tx_done) begin
                                    Send_Go <= 0;
                                    state <= 0;
                                    Trans_Done <= 1;
                                end
                                else begin
                                    Data <= Data;
                                    Send_Go <= 0;
                                    state <= 5;
                                end
                            end
    end
endmodule

方法二:case语句

// Create Date: 2024/04/04 12:08:41
// Design Name: hilary
// Module Name: uart_tx_data

//发送5个字节的数据,40位数据
//两种情况:
//空闲状态:上一次的数据发送完成
//发送数据请求信号到来,从低8位开始,依次发送数据
// 1.等待传输请求信号(Trans_Go)到来
// 2.Data40【7:0】给到uart_byte_tx的Data,同时产生Send_Go信号启动第一个字节的发送
// 3.等待Tx_Done信号二栋到来:① 40位(5个字节)数据是否发送完成
//                          ② 发完了回到1; 没发完启动下一个8位数据的发送

//状态机:
module uart_tx_data2(
    Clk,
    Reset_n,
    Data40,
    Trans_Go,
    uart_tx,
    Trans_Done);

    input Clk;
    input Reset_n;
    input [39:0] Data40;
    input Trans_Go;
    output uart_tx;
    output reg Trans_Done;

    reg Send_Go;
    reg [7:0] Data;
    wire Tx_done;

    uart_byte_tx uart_byte_tx(
        .Clk(Clk),
        .Reset_n(Reset_n),
        .Data(Data),
        .Send_Go(Send_Go),
        .Baud_set(4),
        .uart_tx(uart_tx),
        .Tx_done(Tx_done)
        );
    
    reg [7:0] state;
    always @(posedge Clk or negedge Reset_n) begin
        if (!Reset_n) begin
            state <= 0;
            Data <= 0;
            Send_Go <= 0;
            Trans_Done <= 0;
        end
        else begin
            case (state)
                0: begin
                    Trans_Done <= 0;
                    if(Trans_Go)begin
                        Data <= Data40[7:0];
                        Send_Go <= 1;
                        state <= 1;
                    end
                    else begin
                        Data <= Data;
                        Send_Go <= 0;
                        state <= 0;
                    end
                  end
                
                1: begin
                    if (Tx_done) begin
                        Data <= Data40[15:8];
                         Send_Go <= 1;
                         state <= 2;
                    end
                    else begin
                        Data <= Data;
                        Send_Go <= 0;
                        state <= 1;
                    end
                   end

                2: begin
                    if (Tx_done) begin
                        Data <= Data40[15:8];
                        Send_Go <= 1;
                        state <= 3;
                    end
                    else begin
                        Data <= Data;
                        Send_Go <= 0;
                        state <= 2;
                    end
                   end
                    
                3: begin
                        if (Tx_done) begin
                            Data <= Data40[15:8];
                            Send_Go <= 1;
                            state <= 4;
                        end
                        else begin
                            Data <= Data;
                            Send_Go <= 0;
                            state <= 3;
                        end
                   end

                4: begin
                        if (Tx_done) begin
                            Data <= Data40[23:16];
                            Send_Go <= 1;
                            state <= 5;
                        end
                        else begin
                            Data <= Data;
                            Send_Go <= 0;
                            state <= 4;
                        end
                   end

                5: begin
                        if (Tx_done) begin
                            Send_Go <= 0;
                            state <= 0;
                            Trans_Done <= 1;
                        end
                        else begin
                             Data <= Data;
                            Send_Go <= 0;
                            state <= 5;
                        end
                   end
                default: begin
                        Data <= Data;
                        Send_Go <= 0;
                        state <= 0;
                end
            endcase
    end
    end
    endmodule

测试:

`timescale 1ns / 1ps
// Create Date: 2024/04/04 13:39:50
// Design Name: hilary
// Module Name: uart_tx_data_tb


module uart_tx_data_tb();
    reg Clk;
    reg Reset_n;
    reg [39:0] Data40;
    reg Trans_Go;
    wire uart_tx;
    wire Trans_Done;

    uart_tx_data2 uart_tx_data2(
        Clk,
        Reset_n,
        Data40,
        Trans_Go,      
        uart_tx,
        Trans_Done);

    initial Clk = 1;
    always#10 Clk = ~Clk;

    initial begin
        Reset_n = 0;
        Data40 = 0;
        Trans_Go = 0;
        #201;
        Reset_n = 1;
        #200;
        Data40 = 40 'h123456789a;
        Trans_Go = 1;
        #20;
        Trans_Go = 0;
        @(posedge Trans_Done);
        #200000;

        Data40 = 40 'ha987654321;
        Trans_Go = 1;
        #20;
        Trans_Go = 0;
        @(posedge Trans_Done);
        #200000;
        $stop;
    end    
 
endmodule

结果:

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