module DFF(
r,rb,clk,data,rst
);
output reg r,rb;
input wire data,clk,rst;
//wire load;
//and a1(load,clk,ena);
always @(posedge clk or negedge rst)
if(~rst)
begin
r <= 1'b0;
rb <= 1'b1;
end
else begin
r <= data;
rb <= ~data;
end
endmodule
Verilog语言实现D触发器
最新推荐文章于 2023-06-01 21:00:00 发布