Verilog语言 顺序逻辑练习题1 锁存器和触发器

题目1：
A D flip-flop is a circuit that stores a bit and is updated periodically, at the (usually) positive edge of a clock signal.
D flip-flops are created by the logic synthesizer when a clocked always block is used (See alwaysblock2). A D flip-flop is the simplest form of “blob of combinational logic followed by a flip-flop” where the combinational logic portion is just a wire.
Create a single D flip-flop.
创建一个D触发器。

我的解答：

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//

    // Use a clocked always block
    //   copy d to q at every positive edge of clk
    //   Clocked always blocks should use non-blocking assignments
    
    always@(posedge clk)
        q <= d;

endmodule

题目2：
Create 8 D flip-flops. All DFFs should be triggered by the positive edge of clk.
创建八个D触发器。

我的解答：

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);
    
    always@(posedge clk)
        q[7:0] <= d[7:0];

endmodule

题目3：
创建具有高电平有效同步复位的 8 个 D 触发器。所有 DFF 都应由clk 的上升沿触发。

我的解答：

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);

    always@(posedge clk) begin
        if (reset == 1'b0)
            q <= d;
        else 
            q <= 8'd0;
    end

endmodule

题目4：
Create 8 D flip-flops with active high synchronous reset. The flip-flops must be reset to 0x34 rather than zero. All DFFs should be triggered by the negative edge of clk.
创建具有高电平有效同步复位的 8 个 D 触发器。触发器必须重置为 0x34 而不是零。所有的DFF应由被触发负的边缘CLK。

提示：将寄存器重置为“1”有时称为“预设”。

上升沿为posedge，下降沿为negedge。

我的解答：

module top_module (
    input clk,
    input reset,
    input [7:0] d
    output [7:0] q
);

    always@(negedge clk) begin
        if (reset == 1'b0)
            q <= d;
        else 
            q <= 8'h0x34;
    end
    
    
endmodule

题目5：
Create 8 D flip-flops with active high asynchronous reset. All DFFs should be triggered by the positive edge of clk.
创建具有高电平有效异步复位的 8 个 D 触发器。所有 DFF 都应由clk 的上升沿触发。

提示：同步和异步复位触发器在代码上的唯一区别在于灵敏度列表。

我的解答：

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);
    
    always@(posedge clk,posedge areset)begin
        if (areset)
            q <= 0;
        else
            q <= d;
    end
    
endmodule

题目6：
Create 16 D flip-flops. It’s sometimes useful to only modify parts of a group of flip-flops. The byte-enable inputs control whether each byte of the 16 registers should be written to on that cycle. byteena[1] controls the upper byte d[15:8], while byteena[0] controls the lower byte d[7:0].

resetn is a synchronous, active-low reset.

All DFFs should be triggered by the positive edge of clk.

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);

    always @(posedge clk)begin
        if(resetn == 1'b0)
            q <= 1'b0;
        else begin
            case(byteena)
                2'b01 : q <= {q[15:8],d[7:0]};
                2'b10 : q <= {d[15:8],q[7:0]};
                2'b11 : q <= d;
                default:q <= q;
            endcase
        end
    end
    
endmodule

题目7：
Implement the following circuit:

我的解答：

module top_module (
    input clk,
    input in, 
    output out);

    wire d1;
    
    assign d1 = in^out;
    
    always @(posedge clk)
        out <= d1;
    
endmodule

题目8：
假设您要为该电路实现分层 Verilog 代码，使用其中包含触发器和多路复用器的子模块的三个实例。为此子模块编写一个名为top_module的 Verilog 模块（包含一个触发器和多路复用器）。

这里只要求我们写包含一个触发器和多路复用器的电路。

我的解答：

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q);
    
    wire sel1;
    
    assign sel1 = (L == 1'b0) ? q_in : r_in;
    
    always @(posedge clk) begin
        Q <= sel1;
    end

endmodule

题目8：
Write a Verilog module named top_module for one stage of this circuit, including both the flip-flop and multiplexers.

我的解答：

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
    
    wire sel1;
    wire sel2;
    
    assign sel1 = (E == 1'b0) ? Q : w;
    assign sel2 = (L == 1'b0) ? sel1 : R;
    
    always @(posedge clk) begin
        Q <= sel2;
    end

endmodule

题目9：
Given the finite state machine circuit as shown, assume that the D flip-flops are initially reset to zero before the machine begins.

Build this circuit.

我的解答：

module top_module (
    input clk,
    input x,
    output z
);
    wire xor_in;
    wire and_in;
    wire or_in;
    wire q1;
    wire q2;
    wire q3;
    wire q2n;
    wire q3n;
    
    assign xor_in = q1 ^ x;
    assign and_in = q2n & x;
    assign or_in = q3n | x;
    
    dff_inst dff1(
        .d(xor_in),
        .q(q1),
        .qn(),
        .clk(clk)
    );
    
    dff_inst dff2(
        .d(and_in),
        .q(q2),
        .qn(q2n),
        .clk(clk)
    );
    
    dff_inst dff3(
        .d(or_in),
        .q(q3),
        .qn(q3n),
        .clk(clk)
    );

    assign z = ~(q1|q2|q3);
    
endmodule

module dff_inst (
    input wire d,
    input wire clk,
    output reg q,
    output wire qn
);
    
    always @(posedge clk) begin
        q <= d;
    end
    assign qn = ~q;
    
endmodule   

题目10：
A JK flip-flop has the below truth table. Implement a JK flip-flop with only a D-type flip-flop and gates. Note: Qold is the output of the D flip-flop before the positive clock edge.

我的解答：

module top_module (
    input clk,
    input j,
    input k,
    output Q); 
    
    wire [1:0] sel;
    assign sel = {j,k};
    
    always @(posedge clk) begin
        case (sel)
            2'b00 : Q <= Q;
            2'b11 : Q <= ~Q;
            default :Q <= sel[1];
        endcase
    end

endmodule

题目11：
For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs.

Here are some examples. For clarity, in[1] and pedge[1] are shown separately.

题目要求抓住输入信号的上升沿。则先得到打拍后的信号，再令原信号与打拍后的信号与非后完成抓取输入信号上升沿的目的。

我的解答：

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    
    reg [7:0] in_last;
    
    always @(posedge clk) begin
        in_last <= in;
        pedge <= in & (~in_last);
    end

endmodule

官方解答：

module top_module(
	input clk,
	input [7:0] in,
	output reg [7:0] pedge);
	
	reg [7:0] d_last;	
			
	always @(posedge clk) begin
		d_last <= in;			// Remember the state of the previous cycle
		pedge <= in & ~d_last;	// A positive edge occurred if input was 0 and is now 1.
	end
	
endmodule

题目12：
For each bit in an 8-bit vector, detect when the input signal changes from one clock cycle to the next (detect any edge). The output bit should be set the cycle after a 0 to 1 transition occurs.

Here are some examples. For clarity, in[1] and anyedge[1] are shown separately

分析：
题目想要获取输入信号的双升沿，采用的方式是对输入信号进行打一拍的操作，然后将输入信号与打拍后的信号进行异或就抓取到了输入信号的双升沿，如下图所示

我的解答：

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
    
    reg [7:0] in_edge;
    
    always @(posedge clk) begin
        in_edge <= in;
        anyedge <= in ^ in_edge;
    end

endmodule

题目13：
For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. “Capture” means that the output will remain 1 until the register is reset (synchronous reset).

Each output bit behaves like a SR flip-flop: The output bit should be set (to 1) the cycle after a 1 to 0 transition occurs. The output bit should be reset (to 0) at the positive clock edge when reset is high. If both of the above events occur at the same time, reset has precedence. In the last 4 cycles of the example waveform below, the ‘reset’ event occurs one cycle earlier than the ‘set’ event, so there is no conflict here.

In the example waveform below, reset, in[1] and out[1] are shown again separately for clarity.

此题无头绪，Troke博主解题思路：
其实做法和采集输入信号上升沿的操作非常的类似，先要对输入信号进行打拍，接着也是进行与非的操作，与采集上升沿不同的是，采集下降沿时需要将非号加到输入信号上，其实就是与非左右操作数进行一下交换，这样就可以采集到下降沿。

接着将采集到的下降沿，存到一个临时变量里，然后用for遍历每一位，出现1表示输入信号出现下降沿，此时将数据输出。

Troke博主的解答：

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    /*获取信号的下降沿*/
    reg [31:0] in_reg;             
    always @(posedge clk) begin
        in_reg <= in;
    end
    
    /*将结果寄存到临时的寄存器中*/
    reg		[31:0] 	temp_reg;
	assign temp_reg = ~in&in_reg;
    
    //对每一位进行一个判断，这里需要用到for循环
    always @(posedge clk) begin
        if(reset == 1'b1) 
            out <= 0;
        else begin
            for(int i=0;i<32;i=i+1) begin
                if(temp_reg[i]==1'b1)   //有哪位出现了下降沿，哪位数据发生改变
                    out[i] <= 1'b1;
                else                   //没出现下降沿的保持不变
                    out[i] <= out[i];
            end
        end
    end
endmodule

题目14：
You’re familiar with flip-flops that are triggered on the positive edge of the clock, or negative edge of the clock. A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don’t have dual-edge triggered flip-flops, and always @(posedge clk or negedge clk) is not accepted as a legal sensitivity list.

Build a circuit that functionally behaves like a dual-edge triggered flip-flop:

分析：题目中说FPGA没有双边触发，则说明不能有always@（posedge clk ，negedge clk）这样的书写方式，那么我们可以分开写，分别书写always@（posedge clk）和always@（negedge clk）两个边沿触发，再通过逻辑电路连接起来。

提示：
You can’t create a dual-edge triggered flip-flop on an FPGA. But you can create both positive-edge triggered and negative-edge triggered flip-flops.
This problem is a moderately difficult circuit design problem, but requires only basic Verilog language features. (This is a circuit design problem, not a coding problem.) It may help to first sketch a circuit by hand before attempting to code it.

我的解答：

module top_module (
    input clk,
    input d,
    output q
);
    reg q1;
    reg q2;
    
    always @(posedge clk) begin
        q1 <= d ^ q2;
    end
    
    always @(negedge clk) begin
        q2 <= d ^ q1;
    end
    
    assign q = q1 ^ q2;
            

endmodule

官方解答：

module top_module(
	input clk,
	input d,
	output q);
	
	reg p, n;
	
	// A positive-edge triggered flip-flop
    always @(posedge clk)
        p <= d ^ n;
        
    // A negative-edge triggered flip-flop
    always @(negedge clk)
        n <= d ^ p;
    
    // Why does this work? 
    // After posedge clk, p changes to d^n. Thus q = (p^n) = (d^n^n) = d.
    // After negedge clk, n changes to p^n. Thus q = (p^n) = (p^p^n) = d.
    // At each (positive or negative) clock edge, p and n FFs alternately
    // load a value that will cancel out the other and cause the new value of d to remain.
    assign q = p ^ n;
    
    
	// Can't synthesize this.
	/*always @(posedge clk, negedge clk) begin
		q <= d;
	end*/
    
    
endmodule