verilog练习

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

ENTITY SCHK IS

  PORT(DIN, CLK, CLR  :INSTD_LOGIC;--串行输入数据位/工作时钟/复位信号

        AB :OUTSTD_LOGIC_VECTOR(3DOWNTO0));--检测结果输出

END SCHK;

ARCHITECTURE behav OF SCHK IS

    SIGNAL Q :INTEGERRANGE0TO8;

    SIGNAL D :STD_LOGIC_VECTOR(7DOWNTO0);   --8位待检测预置数

BEGIN

    D <="11100101"  ;--8位待检测预置数：密码：E5H

 Com1:PROCESS( CLK, CLR )

  BEGIN

  IF CLR = '1' THEN    Q <=0;

  ELSIF  CLK'EVENTAND CLK='1' THEN--时钟到来时，判断并处理当前输入的位

     CASE Q IS

      WHEN0=>  IF DIN = D(7)THEN Q <=1;ELSE Q <=0;ENDIF;

      WHEN1=>  IF DIN = D(6)THEN Q <=2;ELSE Q <=0;ENDIF;

      WHEN2=>  IF DIN = D(5)THEN Q <=3;ELSE Q <=0;ENDIF;

      WHEN3=>  IF DIN = D(4)THEN Q <=4;ELSE Q <=0;ENDIF;

      WHEN4=>  IF DIN = D(3)THEN Q <=5;ELSE Q <=0;ENDIF;

      WHEN5=>  IF DIN = D(2)THEN Q <=6;ELSE Q <=0;ENDIF;

      WHEN6=>  IF DIN = D(1)THEN Q <=7;ELSE Q <=0;ENDIF;

      WHEN7=>  IF DIN = D(0)THEN Q <=8;ELSE Q <=0;ENDIF;

      WHENOTHERS=>  Q <=0;

            ENDCASE;

    ENDIF;

  ENDPROCESS;

  Com2:PROCESS( Q )                                 --检测结果判断输出

  BEGIN

      IF Q =8  THEN  AB <="0001";     --序列数检测正确，输出 "1"

      ELSE      AB <="0011";           --序列数检测错误，输出 "3"

      ENDIF;

  ENDPROCESS;

END behav ;