门电路
与门
代码如下
module top_module(
input a,
input b,
output out );
assign out=a&&b;
endmodule
仿真
或非门
module top_module(
input a,
input b,
output out );
assign out=!(a||b);
endmodule
仿真
同或门
module top_module(
input a,
input b,
output out );
assign out= (a&&b)||(!a&&!b);
endmodule
仿真
组合电路
1.二对一多路复用器
module top_module(
input a, b, sel,
output out );
assign out=sel?b:a;
endmodule
仿真
2.半加器
module top_module(
input a, b,
output cout, sum );
assign cout=a&b;
assign sum=a^b;
endmodule
通过真值表判断sum、cout与a、b之间的逻辑关系
3.7420芯片
module top_module (
input p1a, p1b, p1c, p1d,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
assign p1y=!(p1a&&p1b&&p1c&&p1d);
assign p2y=!(p2a&&p2b&&p2c&&p2d);
endmodule
仿真
时序电路
D触发器
module top_module (
input clk, // Clocks are used in sequential circuits
input d,
output reg q );//
// Use a clocked always block
// copy d to q at every positive edge of clk
// Clocked always blocks should use non-blocking assignments
always @(posedge clk)
begin
q<=d;
end
endmodule
仿真
同步复位D触发器
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk)
begin
if(reset)
q=0;
else
q<=d;
end
endmodule
四位二进制计数器
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q);
always @(posedge clk)
begin
if(reset||q[3:0]==1111)
q<=0;
else
q[3:0]<=q[3:0]+1;
end
endmodule