module ALU(
input [2:0] ALU_OP,
input [31:0] A,B,
output reg [31:0] F,
output reg ZF,OF,SF,PF,CF
);
reg C;
always@(*) begin
OF =1'b0;
CF =1'b0;case(ALU_OP)3'b000: begin F = A&B; end
3'b001: begin F = A|B; end
3'b010: begin F = A^B; end
3'b011: begin F =~(A|B); end
3'b100: begin
代码段module ALU( input [2:0] ALU_OP, input [31:0] A,B, output reg [31:0] F, output reg ZF,OF,SF,PF,CF ); reg C; always@(*) begin OF = 1'b0; CF = 1'b0; case(ALU_OP) 3'b000: begin F = A&B; end 3'b001: begin F = A|B; end 3'b010