verilog新入坑注意事项#1

1. 隐式net,(Implicit nets)

 wire [2:0] a, c;   // Two vectors
assign a = 3'b101;  // a = 101
assign b = a;       // b =   1  implicitly-created wire
assign c = b;       // c = 001  <-- bug
my_module i1 (d,e); // d and e are implicitly one-bit wide if not declared.
                    // This could be a bug if the port was intended to be a vector.

添加命令 `default_nettype none
会使得bug 无法编译，也就不会create出line5的一个Implicit net