two-step流程:
Compilation:
vcs [compile_options] Verilog_files
Simultion:
simv [run_options]
three-step流程:
Analysis:verilog和vhdl的命令不同
vlogan [vlogan_options] file1.v file2.v
vhdlan [vhdlan_options] file3.vhd file4.vhd
Elaboration:
vcs [elaboration_options] design_unit
Simulation:
simv [run_options]