Etherlab IGH DC问题

同步时钟有两种方式：
1.使用主站时钟作为整个从机时钟的DC同步方式（同步时间长，误差大）
2.使用第一个带DC的从站作为参考时钟,然后将主站时钟锁定至参考时钟（同步时间短，误差小）以下来自[etherlab-users] DC questions：

Igh-EthercatMaster的dc_user例子里给的是使用主站时钟作为整个从机时钟的DC同步方式a) EtherCAT

master is the master clock:

• The computer is used as the DC master for the entire system.
  ecrt_master_application_time() must be called every cycle to tell the EtherLab master what the current PC time is.
• Call ecrt_master_sync_reference_clock() to tell the slave DC master to sync to the EtherLab masters time.
• Call ecrt_master_sync_slave_clocks() to tell all other DC slaves to sync to the slave DC master

b) Slave DC master is the master clock. What I do is:

• Get the slave DC masters time using ecrt_master_reference_clock_time() and sync the EtherLab masters cycle and time to it
• Call ecrt_master_sync_slave_clocks() to tell all other DC slaves to sync to the slave DC master
• Call ecrt_master_application_time() with the next cycles master timelink 1:http://lists.etherlab.org/pipermail/etherlab-users/2016/003012.htmllink 2:http://lists.etherlab.org/pipermail/etherlab-users/2016/003013.html
• Note: EtherCAT master should have maximum jitter shall be concentrated in the range < 50us, or at the most < 100us, Otherwise DC will not work properly