module configue_dac
(
clk,
rst,
wr_en,
reg_data,
sync,
sclk,
sdata,
state,
cnt,
serial_clk,
reg_load,
reg_latch
);
input clk,rst;
input wr_en;
input [23:0] reg_data;
output sync,sclk,sdata;
//counter///
output [5:0] cnt;
reg [5:0] cnt;
always @(posedge clk or posedge rst)begin
if(rst)
cnt <= 0;
else if(cnt == 6'd50)
cnt <= 0;
else if(cnt_en)
cnt <= cnt + 6'd1;