VHDL数据对象（Data Objects）

数据对象（Data Objects）

数据对象是一个命名项，可以用来表达或存储数据。每个数据对象都有其数据类型和一组唯一的可能值。他们的值取决于该对象定义的数据类型。
An data object is a named item that can be used to represent and store data. Each data object has a specific data type and a unique set of possible values. These values depend on the definition of the data type used for that object.

有以下四种数据对象：
There are four different data objects:

• 常量（Constant）
• 信号（Signal）
• 变量（Variable）
• 共享变量（Shared Variable）

常量（Constant）

常量的值一旦在设计中定义就不允许改变。常量可以被显示声明，或者被显示声明常量的子元素，或者接口常量。在包中定义的常量也可以是延迟常数。
A constant is an object whose value cannot be changed once defined for the design. Constants may be explicitly declared or they may be sub-elements of explicitly declared constants, or interface constants. Constants declared in packages may also be deferred constants.

语法（Syntax）

constant 常量名: 数据类型 [ := 表达式 ]; 

constant constant_name: data_type [ := expression ]; 

说明（Description）

常量用于给一个值命名，方便读取和维护代码。
A constant is used to give a name to a value, this makes it easier to read and maintain the code.

常量声明的数据类型可能是标准或符合类型，也可被约束。常量不能是文件或者访问类型。如果常量是一个数组或者记录，那么其所含元素都不能是文件或访问类型。
The data type in the constant declaration can be of scalar or composite type and it can be constrained. A constant cannot be of the file or access type. If a constant is an array or a record then none of its elements can be of the file or access type.

常量的可见性取决于他们声明的位置。包中定义的常量可以被许多设计单元使用。在设计实体中定义的常量对实体的所有语句和结构体本体可见。在设计单元声明部分定义的常量对和设计相关联的所有单元可见，包括进程语句。进程中定义的常量进队该可在该进程中使用。
The visibility of constants depends on the place of their declaration. The constants defined in the package can be used by several design units. The constant declaration in the design entity is seen by all the statements of the architecture bodies of this entity. The constants defined in the declaration part of the design unit is seen in all bodies related to this design, including the process statement. The constant defined in the process can only be used in this process.

例程（Example）

constant Size: Positive := 8; 
constant MaxSimTime: Time := 200 * ClkPeriod;

注释（Notes）

• 在仿真进程中不能给常量赋值。
• A constant may not be assigned any valuess by the simulation process.
• 使用常量定义数据参数和查找表，可以替代函数调用。以这种方式定义的仿真时间查找表可以显著地缩短函数调用时间。
• Use constants to define data parameters and lookup tables, which may
  substitute function calls. The simulation time of such lookup tables
  is significantly shorter than that of function calls.

信号（Signal）

信号是具有上一历史值得对象。一个信号可以有多个驱动源，每个驱动都有一个当前值和预测的未来值。通过信号声明和端口声明来声明一个信号。
Signal is an object with a past history of values. A signal may have multiple drivers, each with a current value and projected future values. The term signal refers to objects declared by signal declarations and port declarations.

语法（Syntax）

signal 信号名 : 数据类型 [ kind ] [ := 表达式 ]; 

kind = register | bus   -- guarded signal

signal signal_name : data_type [ kind ] [ := expression ]; 

kind = register | bus   -- guarded signal

说明（Description）

信号代表了电器连接、连线或总线。信号用来在进程间通信。
A signal represents an electrical connection, wire or bus. Signals are used for communication between processes.

信号可以在以下几种地方进行声明：
Signals can be explicitly declared in the declarative part of:

• 包声明：在包中声明的信号对使用该包的整个设计实体可见（通过使用use语句）

• package declaration: signals declared in a package are visible in all
  design entities using the package (through the use clause).

• 结构体：结构体声明的信号仅对结构体可见。

• architecture: such signals are visible inside the architecture only.
• 块：块中的信号仅限于块中使用。
• block: the scope of such signals is limited to the block itself.
• 子程序（函数和程序）：子程序中信号仅对子程序有效。
• subprogram (function and procedure): the scope of such signals it
  limited to the subprogram itself.

实体中的端口声明是一种隐式的信号声明。以这种形式声明的信号对分配给该实体的所有结构体可见。
A port declaration in an entity is an implicit signal declaration. A signal declared this way is visible in all architectures assigned to that entity.

可以在信号声明时给他赋初值。如果信号声明时不包含默认值，则其默认值取决于其左边的指定类型。综合时忽略信号的默认值；使用明确的复位来使VHDL和综合后的硬件进入到一个相同的可知状态。
A signal can get a default value in its declaration. If the signal declaration does not contain a default value, then the default value of the signal is the left bound of the specified type. The default value is ignored for synthesis; use an explicit reset to get both the VHDL and the synthesized hardware into the same known state.

使用kind语句声明的信号可以有独立的驱动源不与其解析函数相连。这种信号必须是解析类型。一个寄存器类型的信号没有保存其上一值得驱动器。总线类型的信号以来其解析函数来提供一个“非驱动”值。大部分综合工具忽略解析函数。
A signal declared with a kind statement can have individual drivers disconnected from the resolution function. This signal must be of a resolved type. A register type signal with no drivers connected retains its previous value. The bus type signal relies on the resolution function to supply a “no-drive” value. Most synthesis tools ignore resolution functions.

例程（Example）

signal S1, S2: std_logic_vector(7 downto 0);
signal S3: std_ulogic := '0'; 

变量（Variable）

变量在进程中存储值。
A variable stores a value within a process.

语法（Syntax）

variable 变量名 : 数据类型 [ := 表达式 ]; 

variable variable_name : data_type [ := expression ]; 

说明（Description）

变量用来在进程和子程序（进程和函数）中存储信息。变量的值可以在仿真时通过变量赋值语句来改变。
A variable is an object that stores information local to the process and subprogram (procedures and functions) in which it is defined. A variable’s values can be changed during simulation through the variable assignment statements.

变量的定义包含一个或多个标识符，一个（子）类型指示和一个可选的变量初始值。变量可以被声明为任意可用的类型或子类型，有约束的或者没有约束的。
A variable declaration includes one or more identifiers, a (sub)type indication and an optional initial value for the variable. A variable can be declared to be of any type or sub type available, either constrained or unconstrained.

进程中声明的变量在仿真的一开始被赋以初始值。子程序中的变量在子程序调用时都会被初始化一次。
Variables that are declared in processes are initialized with their default values at the start of the simulation. Variables declared in subprograms are initialized each time the subprogram is called.

变量的作用域仅限于其被定义的进程或子程序。共享变量则不一样，他可以在被许多进程共享。
The scope of variables is limited to the process or subprogram they are defined in. The only exception to this rule is a shared variable, which may be shared by multiple processes.

尽管LRM允许多个进程访问同一个共享变量，但是没有定义当多个相冲突的进程访问同一变量时的情况。这种情况下可能导致不可预料的结果，所以应该避免。
Although the LRM allows several processes to access a single shared variable it does not define what happens when two or more conflicting processes try to access the same variable at the same time. Such a situation may lead to unpredictable results and therefore should be avoided.

例程（Example）

variable V, W: std_logic_vector(7 downto 0);
variable X: integer := 5;

注释（Notes）

• 与信号不同，变量即没有历史值也没有未来值，因为根据其定义，每个变量只有当前值。

• Unlike signals, variables have neither history nor future, because
  according to its definition, each variable has only current value. No
  checking for the last event, time elapsed since the last event,
  previous value, etc. can be performed on variables.

• 如果读取变量值在一个时钟控制的进程中赋值前，则需要在综合时为该变量分配一个寄存器。在一个多进程中出现类似情况，则可能需要一些锁存。

• If a value of a variable is read before it is assigned in a clocked
  process then a register will be synthesized for this variable. A
  similar situation inside a combinatorial process may lead to
  generation of a latch.

• 在子程序中声明的变量被综合为组合逻辑。

• Variables declared in a subprogram are synthesized as combinatorial
  logic.

共享变量（Shared Variable）

共享变量用于进程间通信。
A shared variable is used to share information between processes.

语法（Syntax）

shared variable 变量名 : 数据类型;

shared variable variable_name : data_type;

说明（Description）

共享变量可用于进程间通信。可以在结构体中、块、generate语句和包中声明。
Shared variables can be used to share information between processes. They may be declared within an architecture, block, generate statement, or package.

共享变量可以被多个进程访问。但语言上没有定义如何处理当多个进程同时访问同一共享变量时的情况。
Shared variables may be accessed by more than one process. However, the language does not define what happens if two or more processes make conflicting accesses to a shared variable at the same time.

例程（Example）

shared variable Count: natural;