目录 1. Introduction Link and Lanes Differential 1.1. Signaling rate Bandwidth 2. PCIe Frabric Topology 2.1. Memory Mapped IO 2.2. Transport Model Programmed I/O(PIO) Direct Memory Access(DMA) 3. Layering 4. 4KB Configuration Register Space 4.1. Configuration Space Header 4.2. PCIe Capbility Structure Device/Link Control Register MSI/MSI-X Capability Structures 4.3. PCIe Extended Space 5. Xilinx PCIe IP 5.1. 7 Series Integrated Block for PCI Express 5.2. AXI Memory Mapped To PCI Express IP 5.3. Xilinx DMA/Bridge Subsystem for PCI Express (PCIe)(XDMA) PCIe 学习资源 PCIe总线-PCIe总线简介(一) pcie 详解