Verilog设计模十计数器

module lab02(input clk,input clr,
   output reg[6:0] b);
reg [3:0]q;
always@(posedge clk,negedge clr)
 begin
   if(!clr)
     q<=4'b0000;
   else 
     if (q==4'b1001)
       q<=4'b0000;
     else
       q<=q+1'b1; 
 end 

always@(q)
  begin
   case(q)
   	4'h0:b<=7'b1000000;
   	4'h1:b<=7'b1111001;
	4'h2:b<=7'b0100100;
	4'h3:b<=7'b0110000;
	4'h4:b<=7'b0011001;
	4'h5:b<=7'b0010010;
	4'h6:b<=7'b0000010;
	4'h7:b<=7'b1111000;
	4'h8:b<=7'b0000000;
	4'h9:b<=7'b0010000;
    default:b<=7'b1111111;
    endcase
  end
endmodule

语言环境：Quartus

注意事项：文件命名XXX与module+XXX必须相同

可以在本示例基础上实现多进制计数器