DDR IP工程师

1. Lead/Senior Verification Engineer (Location: SH/BJ)

Position Description:

 Deliver/implement advanced verification solutions by utilizing Cadence’s Incisive Verification product portfolio. The engineer should be able to act as a strong team member and contributor, leading team projects and initiatives. Exercise judgment within generally defined practices and policies.

 Specific duties include:

 Deep understanding on ASIC design and verification flow

 Excellent knowledge of advanced verification methodology like eRM/OVM/UVM/VMM

 Familiar with Cadence’s Incisive Plan to Closure Methodology (IPCM)

 Proficiency in System Verilog, System C and/or e (Specman)

 Developing and using Verification Components (eVC, OVC,UVC,VIP)

 Developing and using assertion based verification and formal analysis methods

 Skilled in scripting language, such as Perl, C shell, Python, Make file

 Assessing the project verification requirements

Position Requirements:

 BS degree with 4+ years of applicable experience, MS degree with 2+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.

 Essential that the individual demonstrates strong communication, verbal and written. Requires good communication skills in English.

 Will have demonstrated hands-on experience and expertise with Cadence verification design tools or equivalent tools, flows and methodologies required to execute a verification project.

 Will have demonstrated successful completion of 3+ verification projects as an individual contributor

 Will have DDR project verification experience

2. Principal/Lead/Senior Physical Design Engineer (Location: SH)

Position Description:

 Focus on high speed digital DDR and HBM IP physical implementation

 Have good physical design experiences in the digital implementation domain including Floorplan, P&R, Physical veri