下图是教材中的例子,教材采用四种方法建模,具体随后道来:
方法一:
(1)、建模
module fsm1(Clock,Reset,A,K1,K2);
input Clock,Reset,A;
output K1,K2;
reg K1,K2;
reg [1:0]state;
//Gray码
parameter Idle=2'b00;
parameter Start=2'b01;
parameter Stop=2'b10;
parameter Clear=2'b11;
always @(posedge Clock)
if(!Reset)
begin
state<=Idle;
K1=0;
K2=0;
end
else
case(state)
Idle:if (A)
begin
state<=Start;
K1<=0;
end
else
begin
state<=Idle;
K1<=0;
K2<=0;
end
Start:if (A)
begin
state<=Start;
K1<=0;
K2<=0;
end
else
begin
state<=Stop;
end
Stop:if (A)
begin
state<=Clear;
K2<=1;
end
else
begin
state<=Stop;
K2<=0;
K1<=0;
end
Clear:if (A)
begin
state<=Clear;
K2<=0;
K1<=0;
end
else
begin
state<=Idle;
K2<=0;
K1<=1;
end
default: state<=2'bxx;
endcase
endmodule
(2)仿真图: