关于LATTICE FIFO_DC的RPReset引脚的解析

What is RPReset port used for in the FIFO_DC module of IP Express?
The RPRESET signal in FIFO_DC component is used as an Active High Reset signal for the Read side.

To read the contents of the FIFO_DC module, the RPRESET signal should be de-asserted, and the RdEn signal should be high to see the valid data on the Q port of the FIFO_DC module.

关于LATTICE FIFO_DC的RPReset引脚的解析。这个引脚在LATTICE MEM文档中都没有介绍。但在网站上找到这样一条。
RPReset为读信号侧时的高有效的信号， 要读出信号时，RPReset信号改成非触发状态，即为低， RDEN信号为高，以读出这个FIFO_DC在Q 端口出现