用CASE语句设计一个功能如74LS138的3线-8线译码器。要求提供代码、RTL图、仿真波形。
代码:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Decord38 IS
PORT(a,b,c : IN STD_LOGIC;
S1,S0a,S0b : IN STD_LOGIC;
Y : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY Decord38;
ARCHITECTURE RTL OF Decord38 IS
SIGNAL q : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
q <= c&b&a;
PROCESS(S1,S0a,S0b,q)
BEGIN
IF(S1='1' AND S0a ='0' AND S0b ='0') THEN
CASE(q) IS
WHEN "000" => Y <= "11111110";
WHEN "001" => Y <= "11111101";
WHEN "010" => Y <= "11111011";
WHEN "011" => Y <= "11110111";
WHEN "100" => Y <= "11101111";
WHEN "101" => Y <= "11011111";
WHEN "110" => Y <= "10111111";
WHEN "111" => Y <= "01111111";
WHEN OTHERS => Y <= NULL;
END CASE;
ELSE Y<= "11111111";
END IF;
END PROCESS;
END ARCHITECTURE RTL;
仿真波形:
RTL图: