[Xilinx FPGA] #10 ISE、Vivado、SDK、HLS 错误记录 [持续记录中]

最新推荐文章于 2022-03-05 20:54:22 发布

Zenor_one

最新推荐文章于 2022-03-05 20:54:22 发布

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分类专栏： [Xilinx FPGA] 文章标签： Vivado

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这里记录的是，在 ISE、Vivado 与 SDK 的日常使用中，笔者遇见过的报错及其解决方法

ISE 14.7

ISE WARNING:ProjectMgmt - File /filePath/ is missing.

有可能原因，在建立工程后，修改了工程名或工程中某模块名称等信息，而 ISE 在重新综合编译时会读取上次综合编译的信息。只需将之前综合编译产生的各文件删除，再重新综合编译即可。这里可使用 ISE 里的 Project - Cleanup Project Files 来清理工程中保留的综合编译信息

Vivado 2017.4

Generate Bitstream 处报错

[Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 4 out of 142 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: USBIND_0_port_indctl[1:0], USBIND_0_vbus_pwrfault, USBIND_0_vbus_pwrselect.
[Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 4 out of 142 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: USBIND_0_port_indctl[1:0], USBIND_0_vbus_pwrfault, USBIND_0_vbus_pwrselect.

解决办法：新建一文件，添加一下内容
set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks RTSTAT-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
重命名为 name.tcl文件（确定后缀格式有效），在 Generate Bitstream 右键进入 Bitstream Settings，在 Write Bitstream 的 tcl.pre* 处添加此文件即可

Linux 环境下，下载器下载时提示被占用

测试硬件时，能发现下载器，但会弹出连接错误
[Labtoolstcl 44-494] There is no active target available for server at localhost. Targets(s) "..." may be locked by another hw_server.

解决办法: 这是因为在有些电脑主板上，需要设置 USB 的兼容性，关闭虚拟机的 Ubuntu，设置 USB 兼容性到“USB3.0”，再次尝试，即可正常使用

SDK 2017.4

通过 vivado 启动 SDK 后没有窗口弹出

可能的原因有：
1. 安装 Vivado 软件的时候一定要安装 SDK，不能先安装 Vivado，再安装 SDK
2. 在启动 SDK 软件前就有 .sdk 目录，可能会导致无法启动 SDK [往往是这个原因，删除这个目录再试即可]

SDK terminal 打印出现乱码

没有任何错误报出，但打印的文字却是乱码，一般这种情况是因为波特率设置不匹配的结果
在 Vivado 中的 Block Design 中的 PS-PL configuration 中可以查看并设置波特率
在 SDK 中，可在 debug configurations - GDB - STDIO connection - Baud rate 处查看并设置串口波特率