Vivado HLS使用与注意事项

作者

QQ群：852283276
微信：arm80x86
微信公众号：青儿创客基地
B站：主页 https://space.bilibili.com/208826118

Vivado HLS 2019.2导出的IP在Vivado中例化丢失管脚

Vivado HLS 2019.2有bug，导出某些ip的时候（有些IP是对的），对应的component.xml丢失管脚，其实.v/.vhd的文件是有这个管脚的，导致在Vivado中综合报错，你可以手动更改component.xml文件。2018.2的版本没有这个问题。

使用HLS IP报错ERROR: [Synth 8-439] module ‘*_frmbuf_rd_0_0_v_frmbuf_rd’ not found

foreach ip_in_proj [get_ips] {compile_c [get_ips $ip_in_proj]}

foreach ip [get_ipdefs] {if {[lsearch [get_property KNOWN_TARGETS [get_ipdefs $ip]] synthesis_c_source]>=1} {puts $ip}}
xilinx.com:ip:v_demosaic:1.0
xilinx.com:ip:v_frmbuf_rd:2.1
xilinx.com:ip:v_frmbuf_wr:2.1
xilinx.com:ip:v_gamma_lut:1.0
xilinx.com:ip:v_hcresampler:1.0
xilinx.com:ip:v_mix:4.0
xilinx.com:ip:v_multi_scaler:1.0
xilinx.com:ip:v_scenechange:1.0
xilinx.com:ip:v_tpg:8.0
get_ips
axis_data_fifo_rx blk_mem_font_yuv422 ila_0 ila_1 system_aurora_64b66b_0_0 system_aurora_64b66b_1_0 system_axi_data_fifo_0_0 system_axi_data_fifo_0_1 system_axi_data_fifo_0_2 system_axi_dma_0_0 system_axi_dma_1_0 system_axi_gpio_0_0 system_axi_interconnect_0_0 system_axi_interconnect_1_0 system_axi_interconnect_1_1 system_axi_interconnect_3_0 system_axi_interconnect_4_0 system_axis_data_fifo_0_0 system_axis_data_fifo_0_1 system_proc_sys_reset_vcu_0_3 system_proc_sys_reset_vcu_1_3 system_time_mark_0_0 system_util_vector_logic_0_0 system_util_vector_logic_0_1 system_v_frmbuf_rd_0_0 system_v_frmbuf_rd_0_1 system_v_frmbuf_rd_0_aresetn1_0 system_v_frmbuf_rd_0_aresetn_0 system_v_frmbuf_rd_0_aresetn_1 system_v_frmbuf_wr_0_0 system_v_frmbuf_wr_0_1 system_v_frmbuf_wr_0_aresetn_0 system_v_frmbuf_wr_1_0 system_v_frmbuf_wr_1_aresetn_0 system_v_mix_0_2 system_v_mix_1_0 system_v_tpg_0_0 system_vcu_0_0 system_vcu_0_aresetn_0 system_vcu_axi_lite_0_3 system_vcu_clk_wiz0_3 system_vcu_interrupt_3 system_xlconcat_0_0 system_xlconcat_0_1 system_xlconstant_0_0 system_xlconstant_0_1 system_xlconstant_0_2 system_xlslice_0_0 system_xlslice_0_1 system_xlslice_aurora0_pma_init_0 system_xlslice_aurora0_pma_init_1 system_xlslice_aurora1_tx_raw_start_en_0 system_xlslice_v_aurora0_aresetn_0 system_xlslice_v_mix_0_0 system_xlslice_v_mix_1_0 system_xlslice_v_mix_2_0 system_zero_0 system_zynq_ultra_ps_e_0_0
compile_c [get_ips system_v_mix_0_2]

2022-04-04，程序总是出错，被xilinx坑惨了，参考Export IP Invalid Argument / Revision Number Overflow Issue (Y2K22)，

source run_ippack.tcl -notrace
bad lexical cast: source type value could not be interpreted as target
    while executing
"rdi::set_property core_revision 2204040059 {component component_1}"
    invoked from within
"set_property core_revision $Revision $core"
    (file "run_ippack.tcl" line 1191)
INFO: [Common 17-206] Exiting Vivado at Mon Apr  4 00:59:45 2022...
ERROR: [IMPL 213-28] Failed to generate IP.
command 'ap_source' returned error code
    while executing
"source c:/Users/zc/AppData/Roaming/Xilinx/Vivado/runhls.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel \#0 [list source $arg] "

# 在D:\Xilinx，右键 > 在windows terminal中打开
PS D:\Xilinx> Vivado\2019.1\tps\win64\python-2.7.5\python.exe y2k22_patch\patch.py
[2022-04-04] INFO: This script (version: 1.2) patches Xilinx Tools for HLS Y2k22 bug for the following release:
                2014.*, 2015.*, 2016.*, 2017.*, 2018.*, 2019.*, 2020.* and 2021.*
[2022-04-04] UPDATE: D:\Xilinx\Vivado\2018.2\common\scripts
[2022-04-04] COPY: D:\Xilinx/y2k22_patch/automg_patch_20220104.tcl  to D:\Xilinx\Vivado\2018.2\common\scripts\automg_patch_20220104.tcl
[2022-04-04] UPDATE: D:\Xilinx\Vivado\2019.1\common\scripts
[2022-04-04] COPY: D:\Xilinx/y2k22_patch/automg_patch_20220104.tcl  to D:\Xilinx\Vivado\2019.1\common\scripts\automg_patch_20220104.tcl