原文地址:VCS使用ABC—如何仿真、dumpFsdb文件、产生coverageReport、查看coverage作者:bright831224
VCS是IC前端设计验证的必备工具之一,这篇可以作为入门使用指南。首先把正文需要的三个文件黏贴在此。
tb_top.v:
module tb_top();
reg clk, rst;
wire [3:0] out;
always #5 clk=~clk;
initial
begin
rst=1'b0;
clk=1'b0;
#30;
rst=1'b1;
#100;
$finish;
end
always@(out)
$display("counter is %d",out);
counter(.reset(rst),
.clk(clk),
.q(out));
endmodule
counter.v:
module counter(reset,clk,q);
input reset,clk;
output[3:0] q;
reg[3:0]q;
reg[3:0]count;
always@(posedge clk)
if(!reset) q<=4'b0;
else if(q==4'b1111)
q<=4'b0;
else
q<=q+1;
endmodule
run_vcs.tcl:
config timebase 1ns
scope tb_top
run 1ns
call $fsdbDumpfile("counter.fsdb");
call $fsdbDumpvars(0,tb_top);
call $fsdbDumpSVA;
# Run to completion
run
quit
VCS 基本用法
分步(编译,然后仿真):
vcs -R tb_top.v counter.v
simv
一步(编译+仿真):
vcs -R tb_top.v counter.v
Compiler version K-2015.09-SP2-10; Runtime version K-2015.09-SP2-10; Mar 30 10:59 2017
counter is 0
counter is 1
counter is 2
counter is 3
counter is 4
counter is 5
counter is 6
counter is 7
counter is 8
counter is 9
counter is 10
$finish called from file "tb_top.v", line 17.
$finish at simulation time 130
V C S S i m u l a t i o n R e p o r t
Time: 130
CPU Time: 0.470 seconds; Data structure size: 0.0Mb
Thu Mar 30 11:00:08 2017
CPU time: .102 seconds to compile + .033 seconds to elab + .160 seconds to link + .653 seconds in simulation
VCS+Verdi用
vcs -R -fsdb tb_top.v counter.v -ucli -do run_vcs.tcl
verdi -F counter.f -ssf counter.fsdb
VCS 跑coverage
VCS跑coverage的用法非常简单,只要-cm加 coverage种类选项就可以,这里我只加了line和branch的coverage
vcs -R -fsdb -ucli -do run_vcs.tcl tb_top.v counter.v -cm line+branch
urg -dir simv.vdb
执行上面两条命令后就会在仿真目录得到urgReport/目录,里面内容是:
css/ dashboard.html hierarchy.html js/ mod0.html mod1.html modlist.html session.xml tests.html
在IE浏览器里打开,我们可以看到line coverage是80%,因为always语句里面5行cover了4行,branch coverage是66%,因为3个分支cover了两个。根据上面仿真波形,很容易看出来 elseif(q==4’b1111)那个分支语句cover不到,因为计数器从0-a还没有到4’b1111。
还有一种查看coveragereport的方式是使用GUI界面(注意:在dve和verdi cov中counter block的line coverage都变成了100,是因为我exclude了line9 q<=4’b0,注意load exlude file有两者方式,方式一load一个*.el的文件:菜单File->load Exclusions->load ExclutionFromFile,方式二load一个*.el文件列表:菜单File->load Exclusions->FromFileList):
dve -cov -dir ./simv.vdb
verdi -cov -covdir ./simv.vdb
最近组内需要用SVA,所以我在这个实验基础上增加 assert 的coverage,其他文件保持不变,counter.v加了一句assertion p1 看下图仿真结果(verdi果然牛叉,连哪些fail和success的assert try都标识出来了,我这里有13次try,成功了3次,分别在下图波形的3个mark处,coverage的报告里面也有体现):
vcs -sverilog -R -fsdb -ucli -do run_vcs.tcl -cm line+branch+assert tb_top.v counter.v
module counter(reset,clk,q);
input reset,clk;
output[3:0] q;
reg[3:0]q;
reg[3:0]count;
always@(posedge clk)
if(!reset) q<=4'b0;
else if(q==4'b1111)
q<=4'b0;
else
q<=q+1;
property p1;
@ (posedge clk) (q[0] ##[1:5] q[1]);
endproperty
a1: assert property(p1);
endmodule
vcs 查看coverage
转自https://www.bbsmax.com/A/Vx5MjL7gdN/
1. compile & simulate
Design compiler & simulate
#!/bin/csh -f
setenv NOVAS_HOME /EDASynopsys/verdi3-I-201403-SP1
setenv NOVAS_PLI ${NOVAS_HOME}/share/PLI/VCS/LINUX64
setenv LD_LIBRARY_PATH $NOVAS_PLI
setenv NOVAS "${NOVAS_HOME}/share/PLI/VCS/LINUX64"
#用于fsdb波形文件dump
setenv novas_args "-P $NOVAS/verdi.tab $NOVAS/pli.a "
vcs +v2k -sverilog +vcs+lic+wait -full64 -debug_pp \
+warn=noCDNYI,noIPDW,noILLGO,noTMR,noPHNE,noIRIID-W \
-Mupdate +notimingcheck +nospecify \
${novas_args}\
-f file.f \
-cm cond+fsm+line \ #VCS creates the simv.vdb directory (the coverage metrics database)
./simv -cm cond+fsm+line #simulate
生成默认的simv.vdb目录,coverage的数据就在里面