//HLS数据类型: ap_fixed<总位宽,整数位宽>
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(优化)Directive (函数/类 -> 变量/对象)Insert Directive
(优化措施 ug902->design optimization)Directive
:DATA_PACK 对结构体打包
:INTERFACE 对接口优化
:RESOURCE
:STREAM
Destination
:Source File 对工程下所有solution
:Directive File 对当前solution
Options
:mode->ap_ovld(对应优化措施)
//:register
//:depth
:port->led_o(userport)
//:clock name
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Run simulation->C simulation dialog->Options:Clean Build
协同modelsim仿真:solution->run c/rtl simulation->Co simulation dialog
->simulator select:modelsim
/rtl select:verilog
/options->dump trace
输出目录:explorer->solution->sim->...
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(HLS导出ip)工具栏->Export RTL->dialog->configure->name:[ip_name]
输出目录:explorer->solution->impl->ip->XX.zip
(在vivado中导入ip)copy XX.zip->ip_repo
新建工程下tools->report->upgrade
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在.xde中的时钟时序约束:create_clock -name clk100Mhz -period 10.0 [get_ports {i_clks}]
...引脚约束:set_proparty PACKGE_PIN Y9 [get_ports {i_clk}]
set_proparty IOSTANDARD LVCMOS33 [get_ports {i_clk}]