VHDL学习笔记——数码管

输入输出映射关系

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity shumaguan is
	port(
		i_time_val:in std_logic_vector(3 downto 0);
		i_sys_res:in std_logic;
		o_guan_display_val:out std_logic_vector(6 downto 0)
	);
end entity shumaguan;
architecture behavel of shumaguan is
	signal r_guan_display_val: std_logic_vector(6 downto 0);
	begin
		process(i_sys_res, i_time_val)
			begin
				if(i_sys_res='1')then
					r_guan_display_val<="0000000";--中间变量
				else
					case i_time_val is
						when "0000" => r_guan_display_val <="1000000";
						when "0001" => r_guan_display_val <="1111001";
						when "0010" => r_guan_display_val <="0100100";
						when "0011" => r_guan_display_val <="0110000";
						when "0100" => r_guan_display_val <="0011001";
						when "0101" => r_guan_display_val <="0010010";
						when "0110" => r_guan_display_val <="0000010";
						when "0111" => r_guan_display_val <="1111000";
						when "1000" => r_guan_display_val <="0000000";
						when "1001" => r_guan_display_val <="0010000";
						when others => r_guan_display_val <="1111111";
						end case;
					end if;
				end process;
				o_guan_display_val<=r_guan_display_val;
end architecture behavel;

仿真波形：