异步信号同步和边沿检测

异步信号的同步化

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异步信号同步化的目的就是在于消除可能存在的亚稳态

至于什么是异步信号同步化,请自行google…这里直接通过两级寄存器对异步信号处理实现同步化

    reg rx_1,rx_2;
    always@(posedge clk or negedge rst_n)
    if(!rst_n)begin
        rx_1 <= 1'b0;
        rx_2 <= 1'b0;
    end
    else begin
        rx_1 <= rx;//data_in
        rx_2 <= rx_1;
    end

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边沿检测

如何对边沿进行检测呢,同样也是使用两级寄存器来实现,通过两级寄存器的值检测信号的变化,产生标志脉冲

    reg s_0_Temp,s_1_Temp;
    //reg s_2_Temp;
    always@(posedge clk or negedge rst_n)
    if(!rst_n)begin
        s_0_Temp <= 1'b0;
        s_1_Temp <= 1'b0;
        //s_2_Temp <= 1'b0;
    end
    else begin
        s_0_Temp <= signal_in;//第一拍
        s_1_Temp <= s_0_Temp;//第二拍
        //s_2_Temp <= s_1_Temp;//第三拍
    end
    //同时钟域打拍
    wire pedge,nedge;
    assign pedge = !s_1_Temp && s_0_Temp;
    assign nedge = s_1_Temp && !s_0_Temp;

/*
//跨时钟域打拍
    //wire pedge,nedge;
    //assign pedge = !s_2_Temp && s_1_Temp;
    //assign nedge = s_2_Temp && !s_1_Temp;
*/

转载OpenHW开源社区FPGA之亚稳态的分析帖子