真值表:
clr | clk | din[3:0] | dout | qout |
1 | X | X | 0 | 0 |
0 | ↑ | din1[3:0] | din1[3:0] | X |
0 | ↑ | X | din1[2]、din1[1]、din1[0]、X | din1[3] |
0 | ↑ | X | din1[1]、din1[0]、X、X | din1[2] |
0 | ↑ | X | din1[0]、X、X、X | din1[1] |
0 | ↑ | din2[3:0] | qin2[3:0] | din1[0] |
0 | ↑ | X | din2[2]、din2[1]、din2[0]、X | din2[3] |
Verilog代码:
module yiweireg4(cl