FPGA那些事儿---驱动VGA电脑显示器显示代码

//top.v

module top(clk,rst_n,hsync,vsync,red,green,blue);

input clk;
input rst_n;
output hsync;
output vsync;
output green;
output red;
output blue;
wire[9:0]hs_addr;
wire[9:0]vs_addr;
wire valid;
wire clkpixel;
wire[5:0] rom_addr;
wire[63:0] rom_data;
mypll u1(
.inclk0(clk),
.c0(clkpixel));
sync u2(.clk(clkpixel),
       .rst_n(rst_n),
.hsync(hsync),
.vsync(vsync),
.hs_addr(hs_addr),
.vs_addr(vs_addr),
.valid(valid));
//vga_ctrl u3(.clk(clkpixel),
//           .rst_n(rst_n),
//  .valid(valid),
//  .hs_addr(hs_addr),
//  .vs_addr(vs_addr),
//  .red(red),
//  .blue(blue),
//  .green(green));
vga_ct u3(.clk(clkpixel),
       .rst_n(rst_n),
.valid(valid),
.hs_addr(hs_addr),
.vs_addr(vs_addr),
       .rom_addr(rom_addr),
.rom_data(rom_data),
.red(red),
.blue(blue),
.green(green));
myrom u4(
.address(rom_addr),
.clock(clkpixel),
.q(rom_data));

endmodule

//vga_ctrl.v

module vga_ctrl(clk,rst_n,valid,hs_addr,vs_addr,red,blue,green);//vga显示模块，使显示RGB数据与同步信号一致。
input clk,rst_n;
input valid;
input[9:0] hs_addr;
input[9:0] vs_addr;
output red;
output blue;
output green;
reg isrect;
always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
 isrect<=1'b0;
end
else if(vs_addr>=10'd0 && hs_addr<10'd100)
begin
 isrect<=1'b1;
end
else
begin
 isrect<=1'b0;
end
assign red=(isrect &&valid)?1'b1:1'b0;
assign green=(isrect &&valid)?1'b1:1'b0;
assign blue=(isrect &&valid)?1'b1:1'b0;
endmodule

//vga_ct.v

module vga_ct(clk,rst_n,valid,hs_addr,vs_addr,

              rom_addr,rom_data,red,blue,green);//vga显示模块，使显示RGB数据与同步信号一致。
input clk,rst_n;
input valid;
input[9:0] hs_addr;
input[9:0] vs_addr;
input[64:0] rom_data;
//input[5:0] rom_addr;
output red;
output blue;
output green;
output[5:0] rom_addr;
reg[5:0] m;
always @(posedge clk or negedge rst_n)//rom行计数m
if(!rst_n)
begin
 m<=6'b0;
end
else if(vs_addr<10'd64 && valid)
begin
 m<=vs_addr[5:0];
end
else
begin
 m<=6'd0;
end


reg[5:0] n;
always @(posedge clk or negedge rst_n)rom列计数n
if(!rst_n)
begin
 n<=6'b0;
end
else if(hs_addr<10'd64 && valid)
begin
 n<=hs_addr[5:0];
end
else
begin
 n<=6'd0;
end




assign rom_addr[5:0]=m;
assign red=valid?rom_data[6'd63-n]:1'b0;
assign green=valid?rom_data[6'd63-n]:1'b0;
assign blue=valid?rom_data[6'd63-n]:1'b0;

endmodule

//sync.v

module sync(clk,rst_n,hsync,vsync,hs_addr,vs_addr,valid);

input clk;//pixel_clk
input rst_n;
output hsync;
output vsync;
output valid;
output[9:0] hs_addr;
output[9:0] vs_addr;
parameter allhs=10'd800;
parameter allvs=10'd525;
reg[9:0] count_hs;
always @(posedge clk or negedge rst_n)//行像素计数
if(!rst_n)
begin
 count_hs<=10'd0;
end
else if(count_hs==allhs)
begin
 count_hs<=10'd0;
end
else
begin
 count_hs<=count_hs+1'b1;
end


reg[10:0] count_vs;
always @(posedge clk or negedge rst_n)//行计数
if(!rst_n)
begin
 count_vs<=10'd0;
end
else if(count_vs==allvs)
begin
 count_vs<=10'd0;
end
else if(count_hs==allhs)
begin
 count_vs<=count_vs+1'b1;
end


reg isready;
always @(posedge clk or negedge rst_n)//有效区域信号
if(!rst_n)
begin
 isready<=1'b0;
end
else if((count_hs>=10'd145 && count_hs<=10'd784) && (count_vs>=10'd26 && count_vs<=10'd515))
begin
isready<=1'b1;
end
else
begin
isready<=1'b0;
end


assign hsync=(count_hs<=10'd96)?1'b0:1'b1;//行同步信号
assign vsync=(count_vs<=10'd2)?1'b0:1'b1;//场同步信号
assign valid=isready;//图像有效区


assign hs_addr=isready?count_hs-10'd146:10'd0;//列地址
assign vs_addr=isready?count_vs-10'd27:10'd0;//行地址

endmodule

//myrom.v

// megafunction wizard: %ROM: 1-PORT%

// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram 


// ============================================================
// File Name: myrom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************




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//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.




// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module myrom