HDLBits_ Finite State Machines部分(最后四题)

Q2a(Exams/2012 q2fsm)

代码如下：

module top_module (
    input clk,
    input reset,     // synchronous reset
    input w,
    output z);
    
	//状态定义
	parameter A  =  3'b000;
	parameter B  =  3'b001;
	parameter C  =  3'b010;
	parameter D  =  3'b011;
	parameter E  =  3'b100;
	parameter F  =  3'b101;
    reg  [3:1] state ,next_state;
    //状态更新
    always@(posedge clk) begin
        if(reset) begin
            state <= A ;
        end else begin
            state <= next_state ;
        end
    end
    //状态转换条件
	always @(*) begin
        case(state)
			A: next_state = w? B : A ;
			B: next_state = w? C : D ;
			C: next_state = w? E : D ;
			D: next_state = w? F : A ;
			E: next_state = w? E : D ;
			F: next_state = w? C : D ;
			default: next_state = A ;
	    endcase
	end
	//状态机输出
    assign z = ((state == E) || (state == F)) ;
 
endmodule

Q2b(Exams/2012 q2b)

代码如下：

module top_module (
    input [5:0] y,
    input w,
    output Y1,
    output Y3
);
    assign Y1 = w && y[0] ;//state B
    assign Y3 = (~w && y[1]) || (~w && y[2]) || (~w && y[4]) || (~w && y[5]) ;//state D

endmodule

Q2a(Exams/2013 q2afsm)

代码如下：

module top_module (
    input          clk,
    input          resetn,    // active-low synchronous reset
    input  [3:1]   r,         // request
    output [3:1]   g          // grant
); 
 
//状态定义
parameter  A  =  4'b0001;
parameter  B  =  4'b0010;
parameter  C  =  4'b0100;
parameter  D  =  4'b1000;
 
//定义现态和次态
    reg  [3:0]   state,next_state;
//状态机第一段，状态初始化，时序逻辑非阻塞赋值
always @(posedge clk) begin
	if (!resetn) begin
		state <= A;
	end else begin
		state <= next_state;
	end
end
 
//状态机第二段，状态跳转，非阻塞赋值
always @(*) begin
	next_state = state;
	case(state)
        A: next_state = r[1]? B :(r[2]? C: (r[3]? D : A)) ;
        B: next_state = r[1]? B : A;
        C: next_state = r[2]? C : A;
        D: next_state = r[3]? D : A;
		default: next_state = A ;
	endcase
end
 
//状态机第三段，结果输出，组合逻辑
    assign g[1] = (state==B);
    assign g[2] = (state==C);
    assign g[3] = (state==D);
 
endmodule

Q2b(Exams/2013 q2bfsm)

代码如下：

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 
    parameter IDLE = 0 ;
    parameter OUT_F = 1 ;
    parameter X_1 = 2 ;//输入x为1
    parameter X_2 = 3 ;//输入x为0
    parameter X_3 = 4 ;//输入x为1
    parameter OUT_G = 5 ;
    parameter Y_0 = 6 ;
    parameter Y_1 = 7 ;
    parameter Y_00 = 8 ;
    //parameter DONE = 9 ;
    parameter WAIT = 9 ;
    reg [3:0] state , next_state ;
    
    //状态机初始化
	always @(posedge clk) begin
		if (!resetn) begin
			state <= IDLE;
		end else begin
			state <= next_state;
		end
	end
    //状态转换关系
    always@(*) begin
        case(state)
            IDLE: next_state = OUT_F ;
            OUT_F: next_state = X_1 ;
            X_1: next_state = x? X_2 : X_1 ;
            X_2: next_state = x? X_2 : X_3 ;
            X_3: next_state = x? OUT_G : X_1 ;
            OUT_G: next_state = y? Y_1 : Y_0 ;
            Y_1: next_state = Y_1 ;
            Y_0: next_state = y? Y_1 : Y_00 ;
            Y_00: next_state = Y_00 ;
            default: next_state = IDLE ;
        endcase
    end
    //状态机输出
    always@(posedge clk) begin
        if(!resetn) begin
            f <= 1'd0 ;
        end else if(state == IDLE) begin
            f <= 1'd1 ;
        end else begin
            f <= 1'd0 ;
        end
    end
    assign g = (state==OUT_G) || (state==Y_1) || (state==Y_0);
    
endmodule