Fsm1
代码如下:
module top_module(
input clk,
input areset, // Asynchronous reset to state B
input in,
output out);//
parameter A=0, B=1;
reg state, next_state;
always @(*) begin // This is a combinational always block
// State transition logic
case(state)
A:
case(in)
1'b0 : next_state <= B ;
1'b1 : next_state <= A ;
endcase
B:
case(in)
1'b0 : next_state <= A ;
1'b1 : next_state <= B ;
endcase
endcase
end
always @(posedge clk, posedge areset) begin // This is a sequential always block
// State flip-flops with asynchronous reset
if(areset)
state <= B ;
else
state <= next_state;
end
// Output logic
assign out = (state == B);
endmodule
Fsm1
与上一题不同的是,这一题使用同步复位
代码如下:
// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
reg out ;
// Fill in state name declarations
parameter A=0 , B=1 ;
reg present_state, next_state;
//状态更新-每个时钟上升沿更新一次
always @(posedge clk) begin
if (reset) begin
present_state <= B ;
end else begin
present_state <= next_state ;
end
end
//状态变更条件
always @(*) begin
case(present_state)
A:
case(in)
1'b0 : next_state = B ;
1'b1 : next_state = A ;
endcase
B:
case(in)
1'b0 : next_state = A ;
1'b1 : next_state = B ;
endcase
endcase
end
//输出
always @(*) begin
case(present_state)
A : out = 1'b0 ;
B : out = 1'b1 ;
endcase
end
endmodule
FSM2
代码如下:
module top_module(
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
//状态转移
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if(areset) begin
state <= OFF ;
end else begin
state <= next_state ;
end
end
//状态更新
always @(*) begin
case(state)
ON : next_state = k ? OFF : ON ;
OFF : next_state = j ? ON : OFF ;
default : next_state = state ;
endcase
end
//不同状态下的输出
always @(*) begin
case(state)
ON : out = 1'b1 ;
OFF : out = 1'b0 ;
endcase
end
endmodule
FSM2
代码如下:
module top_module(
input clk,
input reset, // Synchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
// State transition logic
case(state)
ON : next_state = k ? OFF : ON ;
OFF : next_state = j ? ON : OFF ;
default : next_state = state ;
endcase
end
//状态转移
always @(posedge clk) begin
// State flip-flops with synchronous reset
if(reset) begin
state <= OFF ;
end else begin
state <= next_state ;
end
end
//不同状态下的输出
always @(*) begin
case(state)
ON : out = 1'b1 ;
OFF : out = 1'b0 ;
endcase
end
endmodule
Fsm3comb
代码如下:
module top_module(
input in,
input [1:0] state,
output [1:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
// State transition logic: next_state = f(state, in)
always @(*) begin
case(state)
A : next_state = in ? B : A ;
B : next_state = in ? B : C ;
C : next_state = in ? D : A ;
D : next_state = in ? B : C ;
default : next_state = state ;
endcase
end
// Output logic: out = f(state) for a Moore state machine
always @(*) begin
case(state)
D : out = 1'b1 ;
default : out = 1'b0 ;
endcase
end
endmodule
Fsm3onehot
代码如下:
module top_module(
input in,
input [3:0] state,
output [3:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = state[0]&(~in) | state[2]&(~in) ;
assign next_state[B] = state[0]&(in) | state[1]&(in) | state[3]&(in) ;
assign next_state[C] = state[1]&(~in) | state[3]&(~in) ;
assign next_state[D] = state[2]&(in) ;
// Output logic:
assign out = (state[D]);
endmodule
Fsm3
代码如下:
module top_module(
input clk,
input in,
input areset,
output out); //
reg [1:0] state , next_state ;
parameter A=0 , B=1 , C=2 , D=3 ;
// State flip-flops with asynchronous reset
always @(posedge clk or posedge areset) begin
if(areset) begin
state <= A ;
end else begin
state <= next_state ;
end
end
// State transition logic
always @(*) begin
case(state)
A : next_state = in ? B : A ;
B : next_state = in ? B : C ;
C : next_state = in ? D : A ;
D : next_state = in ? B : C ;
default : next_state = state ;
endcase
end
// Output logic
assign out = (state == D) ;
endmodule
Fsm3s
代码如下:
module top_module(
input clk,
input in,
input reset,
output out); //
reg [1:0] state , next_state ;
parameter A=0 , B=1 , C=2 , D=3 ;
// State flip-flops with asynchronous reset
always @(posedge clk ) begin
if(reset) begin
state <= A ;
end else begin
state <= next_state ;
end
end
// State transition logic
always @(*) begin
case(state)
A : next_state = in ? B : A ;
B : next_state = in ? B : C ;
C : next_state = in ? D : A ;
D : next_state = in ? B : C ;
default : next_state = state ;
endcase
end
// Output logic
assign out = (state == D) ;
endmodule
Exams/ece241 2013 q4
代码如下:
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
parameter a=0 ,b=1 ,c=2, d=3 ,e=4, f=5;
reg [2:0] state , next_state ;
//状态转移
always @(posedge clk) begin
if(reset) begin
state <= a ;
end else begin
state <= next_state ;
end
end
//状态更新 s[n]表示水位在sn?
always @(*) begin
case(state)
a: next_state = s[1] ? b : a ;//水位低于s1的状态
b: next_state = s[2] ? d : (s[1] ? b : a) ;//水位在s1与s2之间且之前的水位是s1
c: next_state = s[2] ? d : (s[1] ? c : a) ;//水位在s1与s2之间且之前的水位是s2
d: next_state = s[3] ? f : (s[2] ? d : c) ;//水位在s2与s3之间且之前的水位是s2
e: next_state = s[3] ? f : (s[2] ? e : c) ;//水位在s2与s3之间且之前的水位是s3
f: next_state = s[3] ? f : e ;//水位高于s3;
default : next_state = state ;
endcase
end
//不同状态下的输出
always @(*) begin
case(state)
a: {fr3,fr2,fr1,dfr} = 4'b1111 ;
b: {fr3,fr2,fr1,dfr} = 4'b0110 ;
c: {fr3,fr2,fr1,dfr} = 4'b0111 ;
d: {fr3,fr2,fr1,dfr} = 4'b0010 ;
e: {fr3,fr2,fr1,dfr} = 4'b0011 ;
f: {fr3,fr2,fr1,dfr} = 4'b0000 ;
endcase
end
endmodule