HDLBits_Finite State Machines(Fsm hdlc与Exams/ece241 2013 q8)

Fsm hdlc

代码如下：

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);
    parameter NONE = 4'd1,ONE = 4'd2,TWO = 4'd3,THREE = 4'd4,FOUR = 4'd5 ;
    parameter FIVE = 4'd6,SIX = 4'd7,ERROR = 4'd8,FLAG = 4'd9,DISCARD = 4'd10 ;
    reg [3:0]state ,next_state ;
    //状态更新
    always @(posedge clk) begin
        if(reset) begin
            state <= NONE ;
        end else begin
            state <= next_state ;
        end
    end
    //状态转换
    always@(*) begin
        case(state)
            NONE: next_state = in? ONE : NONE ;
            ONE: next_state = in? TWO : NONE ;
            TWO: next_state = in? THREE : NONE ;
            THREE: next_state = in? FOUR : NONE ;
            FOUR: next_state = in? FIVE : NONE ;
            FIVE: next_state = in? SIX : DISCARD ;
            SIX: next_state = in? ERROR : FLAG ;
            ERROR: next_state = in? ERROR : NONE ;
            FLAG: next_state = in? ONE : NONE ;
            DISCARD: next_state = in? ONE : NONE ;
        endcase
    end
    //状态机输出
    always@(posedge clk) begin
        if(reset) begin
            {err,flag,disc} = 3'd0 ;
        end else begin
        	case(next_state)
        	    ERROR: err <= 1'b1 ;
        	    FLAG: flag <= 1'b1 ;
        	    DISCARD: disc <= 1'b1 ;
        	    default: {err,flag,disc} = 3'd0 ;
        	endcase
        end
    end
endmodule

Exams/ece241 2013 q8

代码如下：

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 
    parameter IDLE = 0, INPUT_1 = 1, INPUT_0 = 2, DONE = 3;
    reg [1:0] state , next_state;
    //状态更新
    always@(posedge clk or negedge aresetn) begin
        if(!aresetn) begin
            state <= IDLE ;
        end else begin
            state <= next_state ;
        end
    end
    //状态转换
    always@(*) begin
        case(state)
            IDLE: next_state = x? INPUT_1 : IDLE ;
            INPUT_1: next_state = x? INPUT_1 : INPUT_0 ;
            INPUT_0: next_state = x? DONE : IDLE ;
            DONE: next_state = x? INPUT_1 : INPUT_0 ;
            default: next_state = state ;
        endcase
    end
    //状态机输出
    assign z = (next_state == DONE) ;
endmodule