HDLBits_ Finite State Machines部分(Q6b到Q6)

 Q6b(Exams/m2014 q6b)

 

代码如下：

module top_module (
    input  [3:1]   y,
    input          w,
    output         Y2
);
	//状态定义
	parameter   A  =  3'b000;
	parameter   B  =  3'b001;
	parameter   C  =  3'b010;
	parameter   D  =  3'b011;
	parameter   E  =  3'b100;
	parameter   F  =  3'b101;
	 
	reg  [3:1]   next_state;
	 
	always @(*) begin
		case(y[3:1])
			A: next_state = w? A : B ;
			B: next_state = w? D : C ;
			C: next_state = w? D : E ;
			D: next_state = w? A : F ;
			E: next_state = w? D : E ;
			F: next_state = w? D : C ;
			default: next_state = A ;
	    endcase
	end
	 
	assign Y2 = next_state[2];
 
endmodule

 Q6c(Exams/m2014 q6c)

代码如下：(代码是参考其他人的，不是很懂这题是在干什么)

module top_module (
    input  [6:1]    y,
    input           w,
    output          Y2,
    output          Y4
);
	assign Y2 = ~w & y[1];
	assign Y4 = (w&y[2]) | (w&y[3]) | (w&y[5]) | (w&y[6]); 
 
endmodule

 Q6(Exams/m2014 q6)

代码如下：

module top_module (
    input clk,
    input reset,     // synchronous reset
    input w,
    output z);
    
	//状态定义
	parameter A  =  3'b000;
	parameter B  =  3'b001;
	parameter C  =  3'b010;
	parameter D  =  3'b011;
	parameter E  =  3'b100;
	parameter F  =  3'b101;
    reg  [3:1] state ,next_state;
    //状态更新
    always@(posedge clk) begin
        if(reset) begin
            state <= A ;
        end else begin
            state <= next_state ;
        end
    end
    //状态转换条件
	always @(*) begin
        case(state)
			A: next_state = w? A : B ;
			B: next_state = w? D : C ;
			C: next_state = w? D : E ;
			D: next_state = w? A : F ;
			E: next_state = w? D : E ;
			F: next_state = w? D : C ;
			default: next_state = A ;
	    endcase
	end
	//状态机输出
    assign z = ((state == E) || (state == F)) ;

endmodule