嵌入式系统之Y-Chart

在系统设计的模型里面有一个模型称之为Y-chart，其中有一个就称之为Gajski   Y-Chart：

        三个设计展示： 行为；结构； 物理

        四个抽象层次：电路； 逻辑； 处理器（RTL）层次； 系统层次

        四组库：晶体管； 逻辑； RTL； 处理器/通信

Y-Chart如下图，理解整个图，就差不多理解了整个系统设计的理念，我现在只是到了系统层次的表面阶段，还有很长的路要走！

还有一种叫做Stack of Y-Chart：

设计方法论（design methodology）：Design methodology is a sequence of design models,components and tools used to design the product.Methodologies evolve with technology, complexity,and automation.A methodology depends on application, company and design group focus.Standardization arrives when the cost of being special is too high.

Bottom-up Methodology（自顶向下的方法论）：从底层出发

            Pros
                   Abstraction levels clearly separated with its own library
                   Accurate metric estimation with layout on each level
                   Globally distributed development possible
                   Easy management
           Cons
                   An optimal library for each design is difficult to predict
                   All possible components with all possible parameters
                   All possible optimizations for all possible metrics
                   Library customization is outside the design group
                   Layout is performed on every level

Top-down Methodology（自顶向上的方法论）：从最上层出发

             Pros
                    Highest level of customization possible on each abstraction level
                    Only one small transistor library needed
                    Only one layout design at the end
            Cons
                    Difficult metric estimation on upper levels since layout is not known until the end
                    Design decision impact on higher level not clear
                    Hot spot removal is difficult
                    Metric annotation (closure) from lower to higher levels needed during design iterations

Meet-in-the-Middle Methodology（从中间某一级开始的方法论）

           Combines top-down and bottom-up
           Synthesis vs. layout compromise
           Processor level is where they meet
           MoC is synthesized into processor components
           Processor components are synthesized with RTL library
           System layout is generated with RTL components

               Pros
                      Shorter synthesis
                      Less layout
                      Less libraries
                      Better metric closure
              Cons
                      Still needs libraries
                      More then one layout
                      Metric closure still needed
                      Library components may not be optimal

Platform Methodology（平台方法论）
                 Pros
                 Two types of layout: system layout for platform (could be predefined) and standard cell layout for custom components
                 Standard processors are available
                 Custom and interface components are added for optimization
                 Cons
                 Platform customization is still needed
                 SW and IF components synthesis required

System Methodology（系统方法论）
                Pros
                Processor-level component only
                Single retargetable compiler for all architecture cells
                Processor-level layout
                Methodology for application experts
                Minimal knowledge of system and processor levels
               Cons
               Architecture cell definition and library
               IS definition
               Change of mind

FPGA Methodology（fpga方法论）
               Starts with system structure
               Processor components synthesized with RTL and logic components
               Components implemented with LUT and BRAMs
               Layout only once
               Metric estimation very difficult
               Estimation is hidden in the FPGA supplier tools

注：以上内容来自于嵌入式系统鼻祖大牛们的课程PPT！