位拆分与运算

 

`timescale 1ns/1ns
module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,
output reg[4:0]out,
output reg validout
);
//*************code***********//
    reg [15:0]d_reg;
    always@(posedge clk or negedge rst)
        if(!rst)begin
            out<=5'b0;
            validout<=1'b0;    //owing validout is an output
            d_reg<=0;           //owing the input must the wire mode
        end
        else case(sel)
                0:begin
                    d_reg<=d;
                    validout<=0;
                    out<=0;
                end
                1:begin
                    validout<=1;
                    out=d_reg[3:0]+d_reg[7:4];
                 end
                2:begin
                    validout<=1;
                    out=d_reg[3:0]+d_reg[11:8];
                end
                3:begin
                    validout<=1;
                    out=d_reg[3:0]+d_reg[15:12];
                end
                default:;
        endcase          
//*************code***********//
endmodule