imx6ul 设备树文件

最新推荐文章于 2023-05-26 18:07:07 发布
最新推荐文章于 2023-05-26 18:07:07 发布
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分类专栏： 嵌入式 imx6ul 文章标签： linux 内核 imx6ul 设备树 dts
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本文链接：https://blog.csdn.net/cao849861802/article/details/111604277
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 这个设备树文件的路径名字为：linux-4.1.15\arch\arm\boot\dts\imx6ul-14x14-evk.dts

然后修改里面的管脚要参照的文件是：linux-4.1.15\arch\arm\boot\dts\imx6ul-pinfunc.h

这个h文件中的内容标识了各个引脚可以配置成什么功能比如：

MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28

MX6UL_PAD_UART4_RX_DATA__I2C1_SDA

这两个，在下划线前面的内容是相同的，也就是这两个其实是一个引脚，可以配置为不同的功能，第一个如果配置了就是普通的gpio1_28，第二个如果配置了就是i2c的sda，然后配置完成后要记得把dts文件中的其他的这个管脚的功能注释掉，不能重复比如用了第二个功能sda，然后第一个引脚功能有人配置过，那么我们就应该吧这个配置注释掉。

配置完成之后去linux-4.1.15这个路径下make dtbs,然后在路径linux-4.1.15\arch\arm\boot\dts\下会生成相应的dtb文件，将需要的dtb文件拷贝到开发板使用

/*
 * Copyright (C) 2015 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/dts-v1/;

#include <dt-bindings/input/input.h>
#include "imx6ul.dtsi"

/ {
	model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
	compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul", "OKMX6UL-C1" ;

	chosen {
		stdout-path = &uart1;
	};

	memory {
		reg = <0x80000000 0x20000000>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x14000000>;
			linux,cma-default;
		};
	};
	leds {
	compatible = "gpio-leds";
	pinctrl-names = "default";
	status = "okay";
	led1{
		label = "led1";
		gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
		default-state = "off";
	};
	led2{
		label = "led2";
		gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
		default-state = "off";
	};
	led3{
		label = "heartbeat";
		gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
		linux,default-trigger = "heartbeat";
	};
	
	};

	backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm1 0 50000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <6>;
		status = "okay";
	};

	pxp_v4l2 {
		compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
		status = "okay";
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_can_3v3: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "can-3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
		};

		reg_sd1_vmmc: regulator@1 {
			compatible = "regulator-fixed";
			regulator-name = "VSD_3V3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
                        /*gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
			enable-active-high; */
		};

		reg_gpio_dvfs: regulator-gpio {
			compatible = "regulator-gpio";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_dvfs>;
			regulator-min-microvolt = <1300000>;
			regulator-max-microvolt = <1400000>;
			regulator-name = "gpio_dvfs";
			regulator-type = "voltage";
			gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
			states = <1300000 0x1 1400000 0x0>;
		};
	       reg_usb_otg1_vbus: regulator@2 {
			compatible = "regulator-fixed";
		        reg = <2>;
		        pinctrl-names = "default";
		        pinctrl-0 = <&pinctrl_usb_otg1>;
		        regulator-name = "usb_otg1_vbus";
		        regulator-min-microvolt = <5000000>;
		        regulator-max-microvolt = <5000000>;
		        gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
		        enable-active-high;
		 };
	       reg_vref_3v3: regulator@3 {
                        compatible = "regulator-fixed";
                        regulator-name = "vref-3v3";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        reg = <3>;
		};
	};

	sound {
		compatible = "fsl,imx6ul-evk-wm8960",
			   "fsl,imx-audio-wm8960";
		model = "wm8960-audio";
		cpu-dai = <&sai2>;
		audio-codec = <&codec>;
		asrc-controller = <&asrc>;
		codec-master;
		gpr = <&gpr 4 0x100000 0x100000>;
		/*
                 * hp-det = <hp-det-pin hp-det-polarity>;
		 * hp-det-pin: JD1 JD2  or JD3
		 * hp-det-polarity = 0: hp detect high for headphone
		 * hp-det-polarity = 1: hp detect high for speaker
		 */
		hp-det = <3 0>;
                /*hp-det-gpios = <&gpio5 4 0>;
		mic-det-gpios = <&gpio5 4 0>;*/
		audio-routing =
			"Headphone Jack", "HP_L",
			"Headphone Jack", "HP_R",
			"Ext Spk", "SPK_LP",
			"Ext Spk", "SPK_LN",
			"Ext Spk", "SPK_RP",
			"Ext Spk", "SPK_RN",
			"LINPUT2", "Mic Jack",
			"LINPUT3", "Mic Jack",
			"RINPUT1", "Main MIC",
			"RINPUT2", "Main MIC",
			"Mic Jack", "MICB",
			"Main MIC", "MICB",
			"CPU-Playback", "ASRC-Playback",
			"Playback", "CPU-Playback",
			"ASRC-Capture", "CPU-Capture",
			"CPU-Capture", "Capture";
	};

	spi4 {
		compatible = "spi-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_spi4>;
		pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
		status = "okay";
		gpio-sck = <&gpio5 11 0>;
		gpio-mosi = <&gpio5 10 0>;
		cs-gpios = <&gpio5 7 0>;
		num-chipselects = <1>;
		#address-cells = <1>;
		#size-cells = <0>;

		gpio_spi: gpio_spi@0 {
			compatible = "fairchild,74hc595";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0>;
			registers-number = <1>;
			registers-default = /bits/ 8 <0xa7>;
			spi-max-frequency = <100000>;
		};
	};
};

&cpu0 {
	arm-supply = <&reg_arm>;
	soc-supply = <&reg_soc>;
	dc-supply = <&reg_gpio_dvfs>;
};

&clks {
	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <722534400>;
};

&csi {
	status = "okay";
	port {
		csi1_ep: endpoint {
			remote-endpoint = <&ov9650_ep>;
		};
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	status = "okay";
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@2 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <2>;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
		};
	};
};

&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_can_3v3>;
	status = "okay";
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_can_3v3>;
	status = "okay";
};



&gpc {
	fsl,cpu_pupscr_sw2iso = <0x1>;
	fsl,cpu_pupscr_sw = <0x0>;
	fsl,cpu_pdnscr_iso2sw = <0x1>;
	fsl,cpu_pdnscr_iso = <0x1>;
	fsl,wdog-reset = <1>; /* watchdog select of reset source */
	fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
};



&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

         /*RX8010*/
	 rx8010:rtc@32{
		compatible = "epson,rx8010";
		reg = <0x32>;
		};

	 goodix_ts@5d {
		compatible = "goodix,gt9xx";
		reg = <0x5d>;
		status = "disable";
		interrupt-parent = <&gpio5>;
		interrupts = <1 2>;
		goodix,rst-gpio = <&gpio5 0  GPIO_ACTIVE_LOW>; 
		goodix,irq-gpio = <&gpio5 1  GPIO_ACTIVE_LOW>;
		goodix,cfg-group0 = [
				42 D0 02 00 05 05 75 01 01 0F 24 
				0F 64 3C 03 05 00 00 00 02 00 00 
				00 16 19 1C 14 8C 0E 0E 24 00 31 
				0D 00 00 00 83 33 1D 00 41 00 00 
				00 00 00 08 0A 00 2B 1C 3C 94 D5 
				03 08 00 00 04 93 1E 00 82 23 00 
				74 29 00 69 2F 00 5F 37 00 5F 20 
				40 60 00 F0 40 30 55 50 27 00 00 
				00 00 00 00 00 00 00 00 00 00 00 
				00 00 00 00 00 00 00 14 19 00 00 
				50 50 02 04 06 08 0A 0C 0E 10 12 
				14 16 18 1A 1C 00 00 00 00 00 00 
				00 00 00 00 00 00 00 00 00 00 1D 
				1E 1F 20 21 22 24 26 28 29 2A 1C 
				18 16 14 13 12 10 0F 0C 0A 08 06 
				04 02 00 00 00 00 00 00 00 00 00 
				00 00 00 00 00 00 00 00 9C 01];
		goodix,cfg-group2 = [
				48 D0 02 00 05 05 75 01 01 0F 24 
				0F 64 3C 03 05 00 00 00 02 00 00 
				00 16 19 1C 14 8C 0E 0E 24 00 31 
				0D 00 00 00 83 33 1D 00 41 00 00 
				3C 0A 14 08 0A 00 2B 1C 3C 94 D5 
				03 08 00 00 04 93 1E 00 82 23 00 
				74 29 00 69 2F 00 5F 37 00 5F 20 
				40 60 00 F0 40 30 55 50 27 00 00 
				00 00 00 00 00 00 00 00 00 00 00 
				00 00 00 00 00 00 00 14 19 00 00 
				50 50 02 04 06 08 0A 0C 0E 10 12 
				14 16 18 1A 1C 00 00 00 00 00 00 
				00 00 00 00 00 00 00 00 00 00 1D 
				1E 1F 20 21 22 24 26 28 29 2A 1C 
				18 16 14 13 12 10 0F 0C 0A 08 06 
				04 02 00 00 00 00 00 00 00 00 00 
				00 00 00 00 00 00 00 00 3C 01];
	};	
	
	edt_ft5x06@38{
 		compatible = "edt,edt-ft5x06";
		reg = <0x38>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_edt_ft5x06>;
                interrupt-parent = <&gpio5>;
                interrupts = <1 2>;
		status = "disable";
	};

};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	codec: wm8960@1a {
		compatible = "wlf,wm8960";
		reg = <0x1a>;
		clocks = <&clks IMX6UL_CLK_SAI2>;
		clock-names = "mclk";
		wlf,shared-lrclk;
	};

	ov9650: ov9650@30 {
		compatible = "ovti,ov9650";
		reg = <0x30>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_csi1>;
		clocks = <&clks IMX6UL_CLK_CSI>;
		clock-names = "csi_mclk";
		pwn-gpios = <&gpio_spi 6 1>;
		rst-gpios = <&gpio_spi 5 0>;
		csi_id = <0>;
		mclk = <24000000>;
		mclk_source = <0>;
		status = "disable";
		port {
			ov9650_ep: endpoint {
				   remote-endpoint = <&csi1_ep>;
			};
		};
	};

};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog_1>;
	imx6ul-evk {
		pinctrl_hog_1: hoggrp-1 {
			fsl,pins = <
				MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059 /* SD1 CD */
				MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT	0x17059 /* SD1 VSELECT */
				/*MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059*/ /* SD1 RESET */
				MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x80000000
				MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x3008
				MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
				MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x3008
				MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x3008
				MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x3008
				MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x3008
				MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x3008  
				MX6UL_PAD_NAND_DATA05__GPIO4_IO07 0x3008
				MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x3008
				MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3008
				MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x3008
				MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x3008
			>;
		};
				
		pinctrl_csi1: csi1grp {
			fsl,pins = <
				MX6UL_PAD_CSI_MCLK__CSI_MCLK		0x1b088
				MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK	0x1b088
				//MX6UL_PAD_CSI_VSYNC__CSI_VSYNC		0x1b088
				//MX6UL_PAD_CSI_HSYNC__CSI_HSYNC		0x1b088
				//MX6UL_PAD_CSI_DATA00__CSI_DATA02	0x1b088
				//MX6UL_PAD_CSI_DATA01__CSI_DATA03	0x1b088
				//MX6UL_PAD_CSI_DATA02__CSI_DATA04	0x1b088
				//MX6UL_PAD_CSI_DATA03__CSI_DATA05	0x1b088
				//MX6UL_PAD_CSI_DATA04__CSI_DATA06	0x1b088
				//MX6UL_PAD_CSI_DATA05__CSI_DATA07	0x1b088
				//MX6UL_PAD_CSI_DATA06__CSI_DATA08	0x1b088
				//MX6UL_PAD_CSI_DATA07__CSI_DATA09	0x1b088
			>;
		};

		pinctrl_dvfs: dvfsgrp {
			fsl,pins = <
				MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x79
			>;
		};
		pinctrl_usb_otg1_id: usbotg1idgrp {
		        fsl,pins = <
	             		MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
	              >;
	        };
		pinctrl_usb_otg1: usbotg1grp {
			fsl,pins = <
				MX6UL_PAD_LCD_HSYNC__GPIO3_IO02			0x10b0
                  >;
                };

		pinctrl_enet1: enet1grp {
			fsl,pins = <
				MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
				MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
				MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
				MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
				MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
				MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
				MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
				MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
			>;
		};

		pinctrl_enet2: enet2grp {
			fsl,pins = <
				MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
				MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
				MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
				MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
				MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
				MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
				MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
				MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
				MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
				MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
			>;
		};

		pinctrl_flexcan1: flexcan1grp{
			fsl,pins = <
				MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
				MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
			>;
		};

		pinctrl_flexcan2: flexcan2grp{
			fsl,pins = <
				MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
				MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0
				MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0
				MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0
			>;
		};

		pinctrl_lcdif_dat: lcdifdatgrp {
			fsl,pins = <
				MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
				MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
				MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
				MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
				MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
				MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
				MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
				MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
				MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
				MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
				MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
				MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
				MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
				MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
				MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
				MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
				//MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
				//MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
				MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
				MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
				//MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
				//MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
				MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
				MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
			>;
		};

		pinctrl_lcdif_ctrl: lcdifctrlgrp {
			fsl,pins = <
				MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x79
				MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
			/*	MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79 */
				MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
				/* used for lcd reset */
			/*	MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79 */
			>;
		};

		pinctrl_pwm1: pwm1grp {
			fsl,pins = <
				MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
			>;
		};
		
		pinctrl_qspi: qspigrp {
			fsl,pins = <
			/*
				MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK      0x70a1
				MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
				MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01   0x70a1
				MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02   0x70a1
				MX6UL_PAD_NAND_CLE__QSPI_A_DATA03     0x70a1
				MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B      0x70a1
				*/
			>;
		};
		
		pinctrl_nand: nandgrp {
			fsl,pins = <
			/*
				MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x70a1
				MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x70a1
				MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x70a1
				MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x70a1
				MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x70a1
				MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x70a1
				//MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x70a1
				//MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x70a1
				//MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x70a1
				MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x70a1
				MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x70a1
				MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x70a1
				MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x70a1
				MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x70a1
				MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x70a1*/
			>;
		};
		

		pinctrl_sai2: sai2grp {
			fsl,pins = <
				MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
				MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
				MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x11088
				MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x11088
				MX6UL_PAD_JTAG_TMS__SAI2_MCLK		0x17088
				MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x17059
			>;
		};

		pinctrl_sim2_1: sim2grp-1 {
			fsl,pins = <
				//MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD		0xb808
				//MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK		0x11
				//MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B		0xb810
				//MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN		0xb810
				//MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD		0xb811
				//MX6UL_PAD_CSI_DATA02__GPIO4_IO23		0x3008
			>;
		};

		pinctrl_spi4: spi4grp {
			fsl,pins = <
				MX6UL_PAD_BOOT_MODE0__GPIO5_IO10	0x70a1
				MX6UL_PAD_BOOT_MODE1__GPIO5_IO11	0x70a1
				MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x70a1
				//MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x80000000
			>;
		};

		pinctrl_tsc: tscgrp {
			fsl,pins = <
				//MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0xb0
				//MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0xb0
				//MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
				//MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0xb0
			>;
		};
		pinctrl_edt_ft5x06: edt_ft5x06grp {
			fsl,pins = <
				MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x1b0b0
			>;
		};		

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
				MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
			>;
		};

		pinctrl_uart2: uart2grp {
			fsl,pins = <
				MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
				MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
			>;
		};

		pinctrl_uart2dte: uart2dtegrp {
			fsl,pins = <
				MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX	0x1b0b1
				MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX	0x1b0b1
				MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS	0x1b0b1
				MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS	0x1b0b1
			>;
		};

		pinctrl_uart3: uart3grp {
			fsl,pins = <
				MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
				MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
			>;
		};
		
		pinctrl_uart4: uart4grp {
			fsl,pins = <
				MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
				MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
			>;
		};		
		
		pinctrl_uart5: uart5grp {
			fsl,pins = <
				MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
				MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
				//MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x1b0b1
			>;
		};		
	
		pinctrl_uart6: uart6grp {
			fsl,pins = <
				
				MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
				MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
				//MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b1
				/*
				MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x1b0b1
				MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x1b0b1
				*/
			>;
		};	

		pinctrl_uart7: uart7grp {
			fsl,pins = <
				/*
				MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x1b0b1
				MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x1b0b1  
				*/
				MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1
                MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1	
				//MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b1
			>;
		};
	
		pinctrl_uart8: uart8grp {
			fsl,pins = <
				/*
				MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b1 
				MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b1
				*/
				MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x1b0b1
				MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x1b0b1
			>;
		};
		
		pinctrl_adc1: adc1grp {
                         fsl,pins = <
                                //MX6UL_PAD_GPIO1_IO01__GPIO1_IO01   0xb0
                                //MX6UL_PAD_GPIO1_IO02__GPIO1_IO02   0xb0
                                //MX6UL_PAD_GPIO1_IO03__GPIO1_IO03   0xb0
                                //MX6UL_PAD_GPIO1_IO04__GPIO1_IO04   0xb0
                         >;
                };		

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10071
				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
			>;
		};

		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
			fsl,pins = <
				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
			>;
		};

		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
			fsl,pins = <
				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
				MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
			>;
		};

		pinctrl_usdhc2_8bit: usdhc2grp_8bit {
			fsl,pins = <
				MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
				MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
				//MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
				//MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
				//MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
				MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
			>;
		};

		pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
			fsl,pins = <
				MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100b9
				MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170b9
				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
				//MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
				//MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
				//MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
				MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
			>;
		};

		pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
			fsl,pins = <
				MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100f9
				MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170f9
				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
				//MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
				//MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
				//MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
				MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
			>;
		};
		pinctrl_wdog: wdoggrp {
			fsl,pins = <
				MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
			>;
		};
	};
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "okay";
};

&pxp {
	status = "okay";
};

&qspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi>;
	status = "okay";
	ddrsmp=<0>;

	flash0: n25q256a@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,n25q256a";
		spi-max-frequency = <29000000>;
		spi-nor,ddr-quad-read-dummy = <6>;
		reg = <0>;
	};
};

&sai2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;

	assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
			  <&clks IMX6UL_CLK_SAI2>;
	assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <0>, <12289600>;

	status = "okay";
};

&sim2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sim2_1>;
	assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>;
	assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>;
	assigned-clock-rates = <240000000>;
	/* GPIO_ACTIVE_HIGH/LOW:sim card voltage control
	 * NCN8025:Vcc = ACTIVE_HIGH?5V:3V
	 * TDA8035:Vcc = ACTIVE_HIGH?5V:1.8V
	 */
	pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
	port = <1>;
	sven_low_active;
	status = "disabled";
};

&tsc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_tsc>;
	xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
	measure-delay-time = <0xffff>;
	pre-charge-time = <0xfff>;
	touchscreen-average-samples = <32>; 
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	/* fsl,uart-has-rtscts; */
	/* for DTE mode, add below change */
	/* fsl,dte-mode; */
	/* pinctrl-0 = <&pinctrl_uart2dte>; */
	status = "okay";
};
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};
&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	//fsl,rs485-gpio-txen = <&gpio1 1 GPIO_ACTIVE_HIGH>;
	//linux,rs485-enable-at-boot-time;
	status = "okay";
};

&uart6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart6>;
	//fsl,rs485-gpio-txen = <&gpio1 4 GPIO_ACTIVE_HIGH>;
	//linux,rs485-enable-at-boot-time;	
	status = "okay";
};

&uart7 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart7>;
	//fsl,rs485-gpio-txen = <&gpio5 8 GPIO_ACTIVE_HIGH>;
	//linux,rs485-enable-at-boot-time;	
	status = "okay";
};

&uart8 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart8>;
	status = "okay";
};



&usbotg1 {
	vbus-supply = <&reg_usb_otg1_vbus>;
	pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usb_otg1_id>;
	dr_mode = "otg";
	srp-disable;
	hnp-disable;
	adp-disable;
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

&usbphy1 {
	tx-d-cal = <0x5>;
};

&usbphy2 {
	tx-d-cal = <0x5>;
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
        cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	keep-power-in-suspend;
	vmmc-supply = <&reg_sd1_vmmc>;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,wdog_b;
};

 

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1. 下载net-snmp包（源码） 官网：Net-SNMP Download：Net-SNMP 我这里下载的是version：5.9.1，文件名：net-snmp-5.9.1.zip 2. 解压net-snmp-5.9.1.zip unzip net-snmp-5.9.1.zip 如果没有unzip命令则安装zip， apt-get install zip 3.配置编译net-snmp cd net-snmp-5.9.1 #./configure后其他选项可以直接回车 #--pre
c语言十六进制打印结构体
cao849861802的博客
05-17 2048
使用十六进制打印结构体的时候发现每次打印都是出来八个字符，如下： typedef struct temp{ int aa; long bb; }TEMP; void printMsg() { int i; TEMP message; char *fp = (char *)&message; for(i = 0; i < sizeof(TEMP); i++) { printf("%02x ",fp+i); }
onos安装
cao849861802的博客
09-13 1360
1.下载网址 onos源码下载 git clone https://gerrit.onosproject.org/onos bazel工具下载
ubuntu apt-get源替换
cao849861802的博客
11-24 1280
1.备份源文件 cp /etc/apt/sources.list /etc/apt/sources.list.bak 2. 修改apt-get源文件 vi /etc/apt/sources.list 删除文件中所有内容，然后替换为如下内容； deb http://mirrors.ustc.edu.cn/ubuntu/ xenial main restricted universe multiverse deb http://mirrors.ustc.edu.cn/ubuntu/ xenia.
imx6ulll设备树
最新发布
07-28
imx6ull设备树是指用于描述i.MX6ULL处理器的硬件配置和功能的设备树文件。根据引用\[1\]中的描述，可以通过复制和重命名imx6ull-14x14-evk.dts文件来创建一个新的设备树文件，例如imx6ull-myimx-emmc.dts。这个设备树文件可以在arch/arm/boot/dts目录下找到。设备树文件中包含了处理器的各种配置信息，如外设的连接和功能。通过对设备树文件的修改，可以实现对硬件的定制和配置。 #### 引用[.reference_title] - *1* [IMX6ULL Linux内核移植](https://blog.csdn.net/dwh1314/article/details/119393408)[target="_blank" data-report-click={"spm":"1018.2226.3001.9630","extra":{"utm_source":"vip_chatgpt_common_search_pc_result","utm_medium":"distribute.pc_search_result.none-task-cask-2~all~insert_cask~default-1-null.142^v91^insert_down28v1,239^v3^insert_chatgpt"}} ] [.reference_item] - *2* *3* [iMX6ULL上手体验](https://blog.csdn.net/hceng_linux/article/details/89913880)[target="_blank" data-report-click={"spm":"1018.2226.3001.9630","extra":{"utm_source":"vip_chatgpt_common_search_pc_result","utm_medium":"distribute.pc_search_result.none-task-cask-2~all~insert_cask~default-1-null.142^v91^insert_down28v1,239^v3^insert_chatgpt"}} ] [.reference_item] [ .reference_list ]

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