hdlbits练习题答案（更新中）

        最近在学习Verilog，发现hdlbits是个挺不错的练习网站。以下是我自己做的答案，希望与大家一起交流、进步。（本博客将持续更新）

• Verilog Language
  • Basics
    • Wire

      module top_module( input in, output out );
          assign out = in;
      endmodule

    • Wire4

      module top_module( input a,b,c, output w,x,y,z );
          assign w = a;
          assign x = b;
          assign y = b;
          assign z = c;
      endmodule

    • notgate

      module top_module( input in, output out );
          assign out = ~in;
      endmodule

    • andgate

      module top_module( input a, input b, output out );
          assign out = a&b;
      endmodule

    • norgate

      module top_module( input a, input b, output out );
          assign out = ~(a|b);
      endmodule

    • xorgate

      module top_module( input a, input b, output out );
          assign out = (a&b)|(~a&~b);
      endmodule

    • wire decl

      module top_module( input a, input b, input c, input d, output out, output out_n   ); 
          wire ab_and,cd_and;
          assign ab_and = a&b;
          assign cd_and = c&d;
          assign out = ab_and | cd_and;
          assign out_n = ~out;
      endmodule

    • 7458

      module top_module