verilog——奇偶校验位

#奇偶校验位
module parity(bus,odd,even);

input [7:0] bus;
output odd;
output even;
assign odd = ^bus;
assign even = ~odd;

endmodule 
#模10加法计数器
module count10(cout,qout,rst_n,clk);

input clk,rst_n;
output reg [3:0] qout;
output cout;

always @ (posedge clk or negedge rst_n)
begin
    if(!rst_n)
        qout <= 0;
    else
        if(qout < 9)
            qout <= qput + 1;
        else
            qout <= 0;
end
assign cout = (qout == 9) ? 1:0;

endmodule