Ripple-Carry Adder

最新推荐文章于 2024-12-10 11:27:18 发布

SEU-RC

最新推荐文章于 2024-12-10 11:27:18 发布

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文章标签： delay input output each module

本文链接：https://blog.csdn.net/chevroletss/article/details/6288984

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本文介绍了一种使用多个全加器模块构建的N位级联进位加法器。通过将每个全加器的进位输出(Cout)连接到下一个全加器的进位输入(Cin)，形成了级联进位加法器。文中还提到，对于N位的级联进位加法器，传播延迟为(2N+1)Δt，随着输入数据位宽的增加，传播延迟也会单调增加。

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It is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each full adder inputs a C_in, which is the C_out of the previous adder. This kind of adder is a ripple carry adder, since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder.

For a N-bit Ripple-Carry Adder, the propagation delay is (2N+1) ∆t. That is, the propagation delay of a N-bit Ripple-Carry Adder will be monotonously increasing according to the bit width of input data.

So, the propagation delay will be very large if the bit width increased to a large number. It’s very slow.

//Edit by Ray@SEU.IC

//Jan 10th, 2011

//Ver. 1.0

//It's a 4-bit ripple-carry adder using 4 Full_Adder

module Ripple_Carry_Adder_Bit(A, B, Cin, Sum, Cout);

input [3:0] A, B;

input Cin;

output [3:0]Sum;

output Cout;

wire Cout_0, Cout_1, Cout_2;

Full_Adder u0(A[0],B[0],Cin, Sum[0], Cout_0);