二分频， Clock Frequency divided by two

---

`timescale 1ns / 1ps
//
// Company: SEU.IC
// Engineer: RAY
//
// Create Date:    19:16:09 03/31/2011
// Design Name: ClockDiv_2
// Module Name:    ClockDiv_2
//
module ClockDiv_2(
     Reset,
     Clock_in,
     Enable_in,
     Clock_div_2_out
     );
    
    input Reset;
    input Clock_in, Enable_in;
    output Clock_div_2_out;
   
     reg Clock_div_2_out;
    
     always @(posedge Clock_in or negedge Reset)
     begin
       if(!Reset)
          Clock_div_2_out <= 0;
          else
            if(Enable_in)
               Clock_div_2_out = ~Clock_div_2_out;
     end

endmodule

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