三分频， Clock Frequency divided by 3

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`timescale 1ns / 1ps
//
// Company: SEU.IC
// Engineer: RAY
//
// Create Date:    19:31:51 03/31/2011
// Design Name: clk_div_3
// Module Name:    clk_div_3
//
module clk_div_3(
    Clock_in,
     Reset,
     Clock_div_3_out
     );
    
    input Clock_in;
    input Reset;
    output Clock_div_3_out;
     
    wire Clock_div_3_out;
    reg [1:0] pos_cnt, neg_cnt;

    always @(posedge Clock_in or negedge Reset)
    begin
      if(!Reset)
                pos_cnt <= 'd0;
      else
                pos_cnt = (pos_cnt == 'd2) ? 'd0 : (pos_cnt + 'd1);
     end
    
     always @(negedge Clock_in or negedge Reset)
    begin
      if(!Reset)
                neg_cnt <= 'd0;
      else
                neg_cnt = (neg_cnt == 'd2) ? 'd0 : (neg_cnt + 'd1);
     end
                 
    assign   Clock_div_3_out = (pos_cnt != 'd2) && (neg_cnt != 'd2);    

endmodule

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