奇分频的两种方式

七分频

方法一：高低电平各占50%

module jifenpin(
						input wire sys_clk,
						input wire rst_n,
						
						output wire  clk7
    );
parameter M=3'd7;    //分频倍数

reg [2:0] count;
reg clk_1;
reg clk_2;

always @ (posedge sys_clk or negedge rst_n)
	if (~rst_n)
		count <= 3'b0;
	else if (count == M-3'd1)
		count <= 3'b0;
	else
		count <=count + 3'd1;
		
always @ (negedge sys_clk or negedge rst_n)   //注意这里用的是时钟下降沿
	if (~rst_n)
		clk_1 <= 1'b0;
	else if (count == (M-3'd1)/2)
		clk_1 <= 1'b1;
	else if (count == (M-3'd1))
		clk_1 <= 1'b0;
	else
		clk_1 <= clk_1;

always @(posedge sys_clk or negedge rst_n)   //时钟上升沿
	if (~rst_n)
		clk_2 <= 1'b0;
	else if (count == (M-3'b1)/2)
		clk_2 <= 1'b1;
	else if (count == (M-3'b1))
		clk_2 <= 1'b0;
	else 
		clk_2 <= clk_2;
	
assign clk7 = clk_1 | clk_2;
	

endmodule

方法2：标志位的形式：如果直接用flag的话，这里是七分频，但是也是一高六低，如果只是要七分频的时长是没问题的，但是对PWM有要求那就不行还需要加代码，或者直接用方式1

module jifenpin(
						input wire sys_clk,
						input wire rst_n,
						
						output reg  clk_flag
    );
parameter M=3'd7;    //分频倍数

reg [2:0] count;

always @ (posedge sys_clk or negedge rst_n)
	if (~rst_n)
		count <= 3'b0;
	else if (count == M-3'd1)
		count <= 3'b0;
	else
		count <=count + 3'd1;
		
always @(posedge sys_clk or negedge rst_n) 
	if (~rst_n)
		clk_flag <= 1'b0;
	else if (count == (M-3'd2))
		clk_flag <= 1'b1;
	else 
		clk_flag <= 1'b0;

endmodule

module vtf_jifenpin;

	// Inputs
	reg sys_clk;
	reg rst_n;

	// Outputs
//	wire clk7;       //方式1
	wire clk_flag;   //方式2

	// Instantiate the Unit Under Test (UUT)
	jifenpin uut (
		.sys_clk(sys_clk), 
		.rst_n(rst_n), 
//		.clk7(clk7)      //方式1
		.clk_flag(clk_flag)  //方式2
	);

	initial begin
		// Initialize Inputs
		sys_clk = 0;
		rst_n = 0;

		// Wait 100 ns for global reset to finish
		#100;
        rst_n=1'b1;
		// Add stimulus here

	end
	always #10 sys_clk =~sys_clk; 
      
endmodule